The PL can be used to implement individual functions at lower energy cost than when executed on the Arm A9 application processors. Less energy per operation is required because when a function is implemented in the PL, data is transferred from operator to operator in a local assembly line fashion using short, low capacitance local connections.
The same function implemented on a processor requires an instruction and data fetch from local caches or external memory and a result to be written back to registers or the memory system over longer, higher capacitance interfaces. When functions require data to be stored in memory, block RAM can be used at lower energy cost than processor caches. The following table summarizes the approximate energy cost for various functions implemented on both the A9 processor and the 7 series programmable logic.
| Operation | PL Resource | Arm A9 Resource | PL energy/OP (pico Joules op mW/GOP/sec) |
|---|---|---|---|
| Logical Op of 2 var | LUT/FF | ALU | 1.3 |
| 32-bit ADD | LUT/FF | ALU | 1.3 |
| 16x16 Mult | DSP | ALU | 8.0 |
| 32-bit Read/Write register | LUTRAM | L1 | 1.4 |
| 32-bit Read/Write AXI register | LUT/FF | AXI | 30 |
| 32-bit Read/Write local RAM | BRAM | L2 | 23.7/17.2 |
| 32-bit Read/Write OCM | AXI/OCM | CPU/OCM | 44 |
| 32-bit Read/Write DDR3 | AXI/DDR | CPU/DDR | 541/211 |
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Typically, the energy cost to read or write external DDR memory is roughly the same and much larger than the operation cost. As a consequence the energy required by functions which require even a small percentage of external access is dominated by the energy cost of the external access and the total cost will be the same in both PL and CPU implementations. Thus a key to minimizing energy cost is to localize data movement to the PL. If space allows, rather than storing data structures off chip, store them in OCM, BRAM, LUTRAM or flip-flops and avoid the use of unnecessary storage. This approach might require code to be restructured to avoid the use of unnecessary buffers.