The overall approach to power management is described in Power Management. The clock generation subsystem facilitates clock disabling and frequency control which affects power consumption.
The PLL power consumption is directly related to the PLL output frequency. The power consumption can be reduced by using a lower PLL output frequency. Power can also be reduced if one or two of the PLLs are not required. For example, if all of the clock generators can be driven by the DDR PLL, then the Arm and I/O PLLs can be disabled to reduce power consumption. The DDR PLL is the only unit that can drive all of the clock generators.
Each clock can be individually disabled when not in use. In some cases, individual subsystems contain additional clock disabling and other power reduction features.