Mismatched Memory Attributes - Mismatched Memory Attributes - 1.15 English - UG585

A physical memory location is accessed with mismatched attributes if all accesses to the location do not use a common definition of all of the following attributes of that location:

• Memory types: strongly-ordered, device, or normal
• Shareability
• Cacheability

The following rules apply when a physical memory location is accessed with mismatched attributes:

1. When a memory location is accessed with mismatched attributes, the only software visible effects are one or more of the following:
   • Uni-processor semantics for reads and writes to that memory location might be lost. This means:
     • A read of the memory location by a thread of execution might not return the value most recently written to that memory location by that thread of execution.
     • Multiple writes to a memory location by a thread of execution which uses different memory attributes might not be ordered in program order.
   • There might be a loss of coherency when multiple threads of execution attempt to access a memory location.
   • There might be a loss of properties derived from the memory type.
2. If the mismatched attributes for a location mean that multiple cacheable accesses to the location might be made with different shareability attributes, then coherency is guaranteed only if each thread of execution that accesses the location with a cacheable attribute performs a clean and invalidate of the location.
3. The possible loss of properties caused by mismatched attributes for a memory location are defined more precisely if all of the mismatched attributes define the memory location as one of:
   • Strongly-ordered memory
   • Device memory
   • Normal inner non-cacheable, outer non-cacheable memory

     In these cases, the only possible software-visible effects of the mismatched attributes are one or more of:

   • A possible loss of properties derived from the memory type when multiple threads of execution attempt to access the memory location
   • A possible re-ordering of memory transactions to the memory location that use different memory attributes, potentially leading to a loss of coherency or uni-processor semantics. Any possible loss of coherency or uniprocessor semantics can be avoided by inserting DMB barrier instructions between accesses to the same memory location that might use different attributes.
4. If the mismatched attributes for a memory location all assign the same shareability attribute to the location, any loss of coherency within a shareability domain can be avoided. To do so, software must use the techniques that are required for the software management of the coherency of cacheable locations between threads of execution in different shareability domains. This means:
   • If any thread of execution might have written to the location with the write-back attribute, before writing to the location not using the write-back attribute, a thread of execution must invalidate, or clean, the location from the caches. This avoids the possibility of overwriting the location with stale data.
   • After writing to the location with the write-back attribute, a thread of execution must clean the location from the caches to make the write visible to external memory.
   • Before reading the location with a cacheable attribute, a thread of execution must invalidate the location from the caches to ensure that any value held in the caches reflects the last value made visible in external memory.

     In all cases:

   • Location refers to any byte within the current coherency granule.
   • A clean and invalidate operation can be used instead of a clean operation, or instead of an invalidate operation.
   • To ensure coherency, all cache maintenance and memory transactions must be completed, or ordered by the use of barrier operations.
5. If all aliases of a memory location that permit write access to the location assign the same shareability and cacheability attributes to that location, and all these aliases use a definition of the shareability attribute that includes all the threads of execution that can access the location, then any thread of execution that reads the memory location using these shareability and cacheability attributes accesses it coherently, to the extent required by that common definition of the memory attributes.