The reset system includes resets generated by hardware, watchdog timers, the JTAG controller, and software. Every module and system in AMD Zynq™ 7000 SoC devices includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PS_POR_B) and the system reset signal (PS_SRST_B).
There are three watchdog timers in the PS that can generate resets. The JTAG controller can generate a reset that only resets the debug portion of the PS and a system-level reset. Software can generate individual sub-module resets or a system-level reset.
Resets are caused by many different sources and go to many different destinations. This chapter identifies all of the resets and either explains their functionality or provides a pointer to another chapter or another document.