GTX Low-Power Serial Transceivers - GTX Low-Power Serial Transceivers - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

GTX low-power serial gigabit transceivers are available in the 7z030, 7z035, 7z045, and 7z100 devices except where noted in the Serial Transceiver Channels by Device/Package table in Zynq 7000 SoC Packaging and Pinout Product Specifications (UG865). The 7z030 has 0 or 4 GTX transceivers, the 7z035/7z045 has 8 or 16, and the 7z100 device has 16 GTX transceivers. Refer to the packaging guide to get the transceiver count for each package type.

The 7z012s and 7z015 devices includes 4 GTP low-power serial transceivers. The GTP transceivers are discussed in GTP Low-Power Serial Transceivers.

Some highlights of the GTX low-power gigabit transceivers include:
  • High-performance transceivers capable of up to 12.5 Gb/s line rates with flipchip packages and up to 6.6 Gb/s with bare-die flipchip packages.
  • Low-power mode optimized for chip-to-chip interfaces.
  • Advanced Transmit pre and post emphasis, and receiver linear (CTLE) and decision feedback equalization (DFE), including adaptive equalization for additional margin

Ultra-fast serial data transmission to optical modules, between ICs on the same PCB, over the backplane, or over longer distances is becoming increasingly popular and important to enable customer line cards to scale to 200 Gb/s. It requires specialized dedicated on-chip circuitry and differential I/O capable of coping with the signal integrity issues at these high data rates.

The AMD Zynq™ 7000 SoC devices transceiver counts range from 0 to 16 transceiver circuits. Each serial transceiver is a combined transmitter and receiver. The various Zynq 7000 serial transceivers can use a combination of ring oscillators and LC tank architecture to allow the ideal blend of flexibility and performance while enabling IP portability across the family members. Lower data rates can be achieved using logic-based oversampling of PL. The serial transmitter and receiver are independent circuits that use an advanced PLL architecture to multiply the reference frequency input by certain programmable numbers between 4 and 25 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation.