Example: Route UART 0 RxD/TxD Signals to MIO Pins 46, 47 - Example: Route UART 0 RxD/TxD Signals to MIO Pins 46, 47 - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)
Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

In this example, the UART 0 RxD and TxD signals are routed through MIO pins 46 and 47. Many other pin options are possible.

  1. Configure MIO pin 46 for the RxD signal. Write 0x0000_12E1 to the slcr.MIO_PIN_46 register:
    1. Route UART 0 RxD signal to pin 46.
    2. Output disabled (set TRI_ENABLE = 1).
    3. LVCMOS18 (refer to the register definition for other voltage options).
    4. Slow CMOS edge (benign setting).
    5. Enable internal pull-up resistor.
    6. Disable HSTL receiver.
  2. Configure MIO pin 47 for the TxD signal. Write 0x0000_12E0 to the slcr.MIO_PIN_47 register:
    1. Route UART 0 TxD signal to pin 47.
    2. 3-state controlled by the UART (TRI_ENABLE = 0).
    3. LVCMOS18 (refer to the register definition for other voltage options).
    4. Slow CMOS drive edge.
    5. Enable internal pull-up resistor.
    6. Disable HSTL receiver.