To reduce the I/O pin count, the controller also supports up to two SPI flash
memories in a shared bus configuration, as shown in the following figure. This
configuration increases the maximum addressable SPI flash memory from 16 MB (24-bit
addressing) to 32 MB (25-bit addressing), but the throughput remains the same as for
single memory mode. Note that in this configuration, the device level XIP mode (read
instruction codes of 0xBB and 0xEB), is not
supported.
The lower SPI flash memory should always be connected if
the linear Quad-SPI memory subsystem is used, and the upper flash memory is
optional. Total address space is 32 MB with a 25-bit address. In IO mode, the MSB of
the address is defined by U_PAGE which is located at bit 28 of register
0xA0. In Linear address mode, AXI address bit 24 determines the
upper or lower memory page. All of the commands will be executed by the device
selected by U_PAGE in I/O mode and address bit 24 in linear mode.