Note: Deep power down only applies to LPDDR2 mode.
Set deep_pwrdwn_reg.deeppowerdown_en=1. The DDRC puts the DRAM into deep
power down as soon as the transaction buffers are empty. If transactions keep arriving
the DDRC never puts the DRAM into deep power down.
deep_pwrdwn_reg.deeppowerdown_en must be reset to 0 to take DRAM out of
deep power down mode. During deep power down exit, the controller performs automatic
DRAM initialization.
In LPDDR2, once deep_pwrdwn_reg.deeppowerdown_en is reset to 0, there is
a wait period (determined by register reg_ddrc_deeppowerdown_to_x1024) before the DRAM
comes out of deep power down. The value from the spec for this register is 500 µs.
Note: Any command that comes in while the DRAM is in deep power down
mode is stored in the CAM and is processed after deep power down exit and DRAM
re-initialization.