DMA Manager - DMA Manager - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

This section describes how to issue instructions to the DMA manager using one of the two APB interfaces available.

When the DMAC is operating in real time, you can only issue the following limited subset of instructions:

DMAGO
Starts a DMA transfer using a DMA channel that the user specifies.
DMASEV
Signals the occurrence of an event, or interrupt, using an event number that the user specifies.
DMAKILL
Terminates a thread.

The appropriate APB interface must be used depending on the security state in which the SLCR register TZ_DMA_NS initializes the DMA manager to operate. For example, if the DMA manager is in the secure state, the instruction using the secure APB interface must be used or the DMAC ignores the instruction. The non-secure APB interface is the suggested port to use to start or restart a DMA channel when the DMA manager is in the non-secure state, however, the secure APB interface can be used in non-secure mode. (Refer to the Security section for more details.) For additional information related to the use of the DMA PL330 controller with Arm TrustZone, refer to Programming ARM TrustZone Architecture on the Zynq-7000 SoC (UG1019).

Before issuing instructions using the Debug Instruction registers or the DBGCMD register, the DBGSTATUS register must be read to ensure that debug is idle, otherwise, the DMA manager ignores the instructions. Refer to the Debug Command register and Debug Status register in Register Details.

When the DMA manager receives an instruction from an APB slave interface, it can take several clock cycles before it can process the instruction — for example, if the pipeline is busy processing another instruction.

Prior to issuing DMAGO, the system memory must contain a suitable program for the DMA channel thread to execute, starting at the address that the DMAGO specifies.