One design consideration when using the PL to access external memory is the total amount of DDR memory bandwidth that is available. One useful metric of DDR bandwidth is the efficiency of the controller. Efficiency is the total data passed through the controller versus its theoretical throughput during a test period. Table 1 and Table 2 list the efficiency the DDR controller under various access types. The system is configured according to Table 3.
| Access Type | Address Pattern | Efficiency (%) |
|---|---|---|
| Reads | Sequential | 97 |
| Reads | Random | 92 |
| Writes | Sequential | 90 |
| Writes | Random | 87 |
| Reads and Writes | Sequential | 87 |
| Reads and Writes | Random | 79 |
From a design planning perspective, accesses tested in the preceding table could be described as optimistic to near-typical values. The random read/write pattern is not worst case as the DDR controller optimization features are still able to improve efficiency; there might be other more pessimistic access patterns. Overall, the DDR controller was designed to have a maximum efficiency of approximately 75%.
The following table lists a DDR efficiency versus burst length example. It illustrates that moderate length bursts do not result in significant DDR efficiency loss. These moderate burst lengths can be useful in latency-sensitive environments where longer bursts can increase latency for higher-priority masters in the system.
| Burst Length | DDR Efficiency (%) |
|---|---|
| 4 | 87 |
| 8 | 87 |
| 16 | 87 |
| System | PL AXI Clock (MHz) | CPU_6x4x (MHz) | CPU_2x (MHz) | DDR_3x (MHz) | DDR_2x (MHz) | DRAM |
DRAM (Mb/s) |
|---|---|---|---|---|---|---|---|
| #1 | 150 | 675 | 225 | 525 | 350 | DDR3 | 1,050 |