Counter Stop Sequence - Counter Stop Sequence - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English
  1. Read back the value of the Counter Control register.
  2. Set DIS bit to 1, while keeping other bits.
  3. Write back to Counter Control register.