BootROM Error Codes - 1.15 English - UG585

The BootROM can detect an error while processing the BootROM Header or while processing the FSBL/User code for decryption and authentication. When a boot failure occurs, the BootROM puts the device into either a secure or non-secure lockdown; an Error Code is normally generated. The BootROM flowchart with error conditions is shown in Figure 1. The error codes are listed in Table 1.

The error code is visible by observing a bit pulse train on the INIT_B pin (secure lockdown) or by reading the slcr.REBOOT_STATUS [BOOTROM_ERROR_CODE] bit field (non-secure lockdown).

1. INIT_B pin observations:
   • In secure mode INIT_B pulses the 16-bit error code.
   • In non-secure mode INIT_B drives Low, indicating a failure. JTAG is enabled.
2. JTAG access to error code register read:
   • When JTAG is enabled, the DAP controller can be used to read the error code in the slcr.REBOOT_STATUS [BOOTROM_ERROR_CODE] register field.

The INIT_B pulses are meant to be visually read with an LED on the INIT_B pin. The pulses are active-High. A long Low pulse on the pin indicates a 1 and a short pulse indicates a 0. The bit order is LSB to MSB. The pulse train is repeated three times. An example pulse train is shown in the following figure using a 60 MHz PS_CLK frequency. The timing will scale linearly with the PS_CLK frequency.

Figure 1. Error Code INIT_B Bit Waveform Example

Non-secure boot failures result in the BootROM disabling access to the AES unit, clearing the PL, and enabling JTAG. The slcr.REBOOT_STATUS register can be read to determine the source of the boot failure.