Boot Time Optimizations - Boot Time Optimizations - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)
Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

To improve NAND boot time, raise the clock rates, and optimize the I/O protocol by setting the registers listed in the following table. The example values might not be appropriate or optimal for all NAND devices or board layouts. The settings assume a 33 MHz PS_CLK. If a faster clock is used, then a larger divider must be considered.

Table 1. NAND Boot Time Optimization Register Setting Example
Register Width Security 1 Value Description
slcr.ARM_CLK_CTRL Both Both 0x1F000200 CPU divisor = 2 (433 MHz)
slcr.SMC_CLK_CTRL Both Both 0x00000921 Baud rate divisor = 9 (96 MHz, 10.4 ns)
smc.set_cycles Both Non-secure 0x00225133

Timing Parameters:

t_rr=2, t_ar=1, t_clr=1, t_wp=2, t_rea=1, t_wc=3, t_rc=3
smc.set_opmode 8-bit Non-secure 0x00000000 8-bit width
16-bit Non-secure 0x00000001 16-bit width
smc.direct_cmd Both Non-secure 0x02400000 Select ModeReg and UpdateRegs
  1. In secure mode, the smc registers are not accessible for optimization using the Register Initialization writes as shown in Table 1.