Boot Time Optimizations - Boot Time Optimizations - 1.15 English - UG585

Zynq 7000 SoC Technical Reference Manual (UG585)

Document_ID
UG585
Release_Date
2026-02-06
Version
1.15 English

To improve the boot time of SD card, set the CPU clock divider to 2 instead of 4. The setting assumes a 33 MHz PS_CLK. If a faster clock is used, then a larger divider must be considered.

Table 1. SD Card Boot Time Optimization Register Setting Example
Register Security Value Description
slcr.ARM_CLK_CTRL Both 0x1F000200 CPU divisor = 2 (433 MHz)