APU and OCM State after BootROM - APU and OCM State after BootROM - 1.15 English - UG585

The general processor state upon BootROM exit is as follows:

• MMU, Icache, Dcache, L2 cache are all disabled.
• Both processors are in the supervisor state.
• ROM code is inaccessible.
• 192 KB of OCM memory is accessible starting at address 0x0000_0000 while the upper 64 KB of the OCM is accessible starting at address 0xFFFF_0000.
• CPU 0 branches into the stage 1 boot image if no failure takes place.
• CPU 1 is in a WFE state while executing code located at address 0xFFFF_FE00 to 0xFFFF_FFF0.