Zynq 7000 SoC Technical Reference Manual (UG585)

Document ID: UG585
Release Date: 2023-06-30
Revision: 1.14 English

Zynq 7000 SoC Technical Reference Manual
Introduction
Overview
Block Diagram
Documentation Resources
Notices
Zynq 7000 SoC Device Family
Device Revisions
TrustZone Capabilities
Processing System (PS) Features and Descriptions
Application Processor Unit (APU)
Dual/Single Arm Cortex-A9 MPCore CPUs with Arm v7
System Features
Memory Interfaces
DDR Controller
DDR Controller Core and Transaction Scheduler
Quad-SPI Controller
Static Memory Controller (SMC)
I/O Peripherals
GPIO
Gigabit Ethernet Controllers (Two)
USB Controllers: Each as Host, Device or OTG (Two)
SD/SDIO Controllers (Two)
SPI Controllers (Two): Master or Slave
CAN Controllers (Two)
UART Controllers (Two)
I2C Controllers (two)
PS MIO I/Os
Programmable Logic Features and Descriptions
Interconnect Features and Description
PS Interconnect Based on AXI High Performance Datapath Switches
PS-PL Interfaces
System Software
Signals, Interfaces, and Pins
Introduction
Notices
7z007s and 7z010 CLG225 Devices
PS-PL Voltage Level Shifters
Pin Timing and Voltage Specifications
Power Pins
PS I/O Pins
7z007s and 7z010 Devices
PS–PL Voltage Level Shifter Enables
Example: Power-up Sequence
Example: Power-down Sequence
PS-PL MIO-EMIO Signals and Interfaces
I/O Peripheral (IOP) Interface Routing
IOP Interface Connections
MIO Pin Assignment Considerations
MIO-at-a-Glance Table
MIO Signal Routing
Default Logic Levels
MIO Pin Electrical Parameters
VREF Source Considerations
PS–PL AXI Interfaces
PS–PL Miscellaneous Signals
Clocks and Resets
Clocks
Resets
Interrupt Signals
Event Signals
Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals
DMA Req/Ack Signals
PL I/O Pins
7z007s and 7z010 Device Notice
Application Processing Unit
Introduction
Basic Functionality
System-Level View
Cortex-A9 Processors
Summary
Central Processing Unit (CPU)
Pipeline
Branch Prediction
Instruction and Data Alignment
Trace and Debug
Level 1 Caches
Initialization of L1 Caches
Memory Ordering
Memory Ordering Model
Device and Strongly Ordered
Normal Memory
Memory Attributes
Shareability
Cacheability
Memory Barriers
Data Memory Barrier (DMB)
Example: Weakly Ordered Message Passing Problem
Data Synchronization Barrier (DSB)
Example: Instruction Cache Maintenance Operations
Instruction Synchronization Barrier (ISB)
Mismatched Memory Attributes
Memory Management Unit (MMU)
MMU Functional Description
Translation Tables
Level 1 Page Tables
Example: Generation of a Physical Address from a L1 Page Table Entry
Level 2 Page Tables
Description of Page Table Entry Fields
Memory Access Permissions (AP and APx)
Memory Attributes (TEX, C and B bits)
Domains
Shareable bit (S)
Non-Global Region Bit (nG)
Execute Never bit (xN)
TLB Organization
Micro TLB
Main TLB
Translation Table Base Register 0 and 1
TLB Match Process
Memory Access Sequence
TLB Maintenance Operations
TLB Lockdown
Interfaces
AXI and Coherency Interfaces
Debug and Trace Interfaces
Other Interfaces
NEON
Performance Monitoring Unit
Snoop Control Unit (SCU)
Summary
Address Filtering
SCU Master Ports
L2-Cache
Summary
Cache Response
Exclusive L2-L1 Cache Configuration
Cache Replacement Strategy
Cache Lockdown
Lockdown by Line
Lockdown by Way
Lockdown by Master
Enabling and Disabling the L2 Cache Controller
RAM Access Latency Control
Store Buffer Operation
Optimizations Between Cortex-A9 and L2 Controller
Early Write Response
Pre-fetch Hints
Full Line of Zero Write
Speculative Reads of the Cortex-A9
Pre-fetching Operation
Programming Model
Initialization Sequence
Cache Lockdown by Way Sequence
APU Interfaces
PL Co-processing Interfaces
ACP Interface
ACP Requests
ACP Usage
ACP Limitations
Event Interface
Interrupt Interface
Support for TrustZone
Application Processing Unit (APU) Reset
Reset Functionality
APU State After Reset
Power Considerations
Introduction
Standby Mode
Dynamic Clock Gating in the L2 Controller
CPU Initialization Sequence
Implementation-Defined Configurations
System Addresses
Address Map
PL AXI Interface Note
Execute-In-Place Capable Devices
System Bus Masters
SLCR Registers
CPU Private Bus Registers
SMC Memory
7z007s and 7z010 Device Notice
PS I/O Peripherals
Miscellaneous PS Registers
Interconnect
Introduction
Features
Block Diagram
Interconnect Masters
Snoop Control Unit (SCU)
Central Interconnect
Master Interconnect
Slave Interconnect
Memory Interconnect
OCM Interconnect
L2 Cache Controller
Interconnect Slaves
Datapaths
Clock Domains
Connectivity
AXI ID
Read/Write Request Capability
Register Overview
Quality of Service (QoS)
Basic Arbitration
Advanced QoS
Rationale
DDR Port Arbitration
AXI_HP Interfaces
Features
Block Diagram
Functional Description
Performance
Register Overview
Bandwidth Management Features
QoS Priority
FIFO Occupancy
Interconnect Issuance Throttling
Write FIFO Store and Forward
32-bit Interface Considerations
Upsizing and Expansion
32-bit Interface Limitations
Transaction Types
Command Interleaving and Re-Ordering
Performance Optimization Summary
AXI_ACP Interface
AXI_GP Interfaces
Features
Performance
PS-PL AXI Interface Signals
AXI Signals
AXI Clocks and Resets
Loopback
Exclusive AXI Accesses
CPU/L2
ACP
DDRC
System Summary
Boot and Configuration
Introduction
PS Master Boot Mode
JTAG Slave Boot
Boot and Configuration Subsections
Device Boot Flowchart
BootROM and Header Parameters
PL Initialization and Configuration
Secure PS Images and PL Bitstreams
Software Developers Guide and Kit
PS Hardware Boot Stages
External PS Control Pins
PS PLL Initialization
PS Software Boot Stages
S t a ge 0 (BootROM: BootROM Header)
S t a ge 1 (FSBL / User code)
S t a g e 2 (U-Boot / System / Application)
Boot Device Content
Boot Modes
Flash Devices (Master Mode Boot)
JTAG (Slave Mode Boot)
BootROM Execution
Secure Boot
BootROM Header Search
BootROM Execution Influencers
Error Detection, Device Lockdown and Error Codes
FSBL / User Code Execution
FSBL Image Fallback and Multiboot
PL Boot Process
PL Configuration Paths
TAP Controller
PCAP Controller
ICAP Controller
Device Configuration Interface
Features
Block Diagram
DevC Control and Status Registers
Interrupts and Status Bits
PCAP Bridge Module
Device Security Module
XADC Interface
Starting Code on CPU 1
Development Environment
Device Start-up
Introduction
Power Requirements
PL Power-Down
Clocks and PLLs
Reset Operations
POR Reset
Non-POR Resets
External Reset Signal Pins
Reset Signal Sequencing
Internal Resets
Reset Reason
System Reset Effects
User Defined Persistent Bit Field
Boot Mode Pin Settings
I/O Pin Connections for Boot Devices
BootROM Code
BootROM Flowchart
Secure/Non-Secure
Boot Sources
APU Initialization
BootROM Header
Interrupt Table for Execution-in-Place — 0x000 to 0x01C
Width Detection — 0x020
Image Identification — 0x024
Encryption Status — 0x028
FSBL/User Defined — 0x02C
Source Offset — 0x030
Length of Image — 0x034
FSB Load Address— 0x038
Start of Execution — 0x03C
Total Image Length — 0x040
QSPI Config Word — 0x044
Header Checksum — 0x048
FSBL/User Defined— 0x04C to 0x097
Boot Header Table Offset — 0x098
QSPI Config Word — 0x09C
Register Initialization Parameters — 0x0A0 to 0x89C
Restricted Addresses
FSBL/User Defined — 0x8A0 - 0x8BF
FSBL Image or User Code Start Address — 0x8C0
BootROM Performance
Typical BootROM Execution
PS PLL Lock Time
Register Initialization to Optimize Boot Times
CRC Check for BootROM Code Option
PL Considerations
PL Power-on Reset Time (TPOR)
PS_POR_B De-assertion Guidelines
AES Decryption and HMAC Authentication
RSA Authentication Time
BootROM and Image Copy Time
Quad-SPI Boot
I/O Configuration Detection
4-bit I/O Detection
8-bit I/O Detection
BootROM Header Search
MIO Programming
Execute-in-Place Option
Configuration Register Settings
Boot Time Optimizations
NAND Boot
Boot Time Optimizations
BootROM Operations
Bad Block Management
ECC Management
Memory Partitions
I/O Signal Timing
NOR Boot
Boot Time Optimizations
SD Card Boot
BootROM Steps
File Partitions
Boot Page Access
BootROM Header Search and Multiboot
Boot Time Optimizations
JTAG Boot
JTAG Enable/Disable Control
Example: JTAG Boot Sequence
Cascaded JTAG Chain Mode
Independent JTAG Chain Mode
EMIO PJTAG Interface for Independent Mode
MIO PJTAG Interface for Independent Mode
MIO Pin States for JTAG Boot Mode
Reset, Boot, and Lockdown States
Reset State
Boot State
Lockdown State
MIO Pin State
BootROM Header Search
BootROM Header Search Stepping and Range
MultiBoot
Multiboot Programming Steps
BootROM Error Codes
Error Code Numbers
Lockdown Types
Post BootROM State
APU and OCM State after BootROM
Memory Map During BootROM Execution
Post BootROM Security
Post BootROM Debug
Registers Modified by the BootROM – Examples
Device Boot and PL Configuration
Basic Boot Sequence
Chapter Sections
PL Control via PS Software
PL Initialization via PS Software
PL Configuration via PS Software
Boot Sequence Examples
Example Sequences
PS Non-secure Bring-up Example
PS Bring-up with PL Configuration Example
PL Bring-up by FSBL/User Code Example
Configure the PL via PCAP Bridge Example
PCAP Bridge to PL
PCAP Datapath Configurations
Non-Secure PL Bitstream
Secure Bitstreams and Software Boot Images
Status Interrupts Bits
PL Bitstream Readback
Example: PL Bitstream Readback
Loopback For Boot Image Transfers
PL Initialization and Configuration Registers
PL Control via User-JTAG
PL User Control and Status Signals
Reference Section
PL Configuration Considerations
PCAP/ICAP/JTAG/User Access Exclusivity
Secure Mode PL Configuration
Determine the PL State
PL Initialization Time Optimization
PCAP Clocking
PCAP Throughput
Boot Time Reference
Register Overview
PS Version and Device Revision
Interrupts
Environment
Private, Shared and Software Interrupts
Generic Interrupt Controller (GIC)
Resets and Clocks
Block Diagram
CPU Interrupt Signal Pass-through
Functional Description
Software Generated Interrupts (SGI)
CPU Private Peripheral Interrupts (PPI)
Shared Peripheral Interrupts (SPI)
Interrupt Sensitivity, Targeting and Handling
Shared Peripheral Interrupts (SPI)
Private Peripheral Interrupts (PPI)
Software Generated Interrupts (SGI)
Wait for Interrupt Event Signal (WFI)
Register Overview
Write Protection Lock
Programming Model
Interrupt Prioritization
Interrupt Handling
Arm Programming Topics
Legacy Interrupts and Security Extensions
Timers
Introduction
System Diagram
Notices
7z007s and 7z007s CLG225 Devices
CPU Private Timers and Watchdog Timers
Clocking
Interrupt to PS Interrupt Controller
Resets
Register Overview
Global Timer (GT)
Clocking
Register Overview
System Watchdog Timer (SWDT)
Features
Block Diagram
Functional Description
Interrupt to PS Interrupt Controller
Reset
Register Overview
Programming Model
System Watchdog Timer Enable Sequence
Clock Input Option for SWDT
Reset Output Option for SWDT
Triple Timer Counters (TTC)
Features
Block Diagram
Functional Description
Modes of Operation
Event Timer Operation
Register Overview
Programming Model
Counter Enable Sequence
Counter Stop Sequence
Counter Restart Sequence
Event Timer Enable Sequence
Interrupt Clear and Acknowledge Sequence
Clock Input Option for Counter/Timer
I/O Signals
DMA Controller
Introduction
Features
System Viewpoint
System Functions
DMA Controller Functions and Programming
Block Diagram
DMA Instruction Execution Engine
Instruction Cache
Read/Write Instruction Queues
Multi-channel Data FIFO
AXI Master Interface for Instruction Fetch and DMA Transfers
APB Slave Interface for Register Accesses
Interrupt Interface
PL Peripheral DMA Request Interface
Reset Initialization Interface
Notices
Arm IP Core
Secure/Non-Secure Modes
Other DMA Controllers
Functional Description
Common to all DMAC operating conditions
Memory-to-memory transfers are managed by the DMAC
When the PL Peripheral Request Interface is used
Advanced DMAC operating features
IP core Configuration
DMA Transfers on the AXI Interconnect
AXI Transaction Considerations
DMA Manager
Example: Start DMA Channel Thread
Multi-channel Data FIFO (MFIFO)
Memory-to-Memory Transfers
PL Peripheral AXI Transactions
Programming Examples
PL Peripheral Request Interface
Handshake Rules
Map PL Peripheral Interface to a DMA Channel
PL Peripheral Request Interface Timing Diagram
PL Peripheral - Length Managed by PL Peripheral
PL Peripheral - Length Managed by DMAC
Events and Interrupts
Aborts
Security
Nomenclature
Security by DMA Manager
Security by DMA Channel Thread
IP Configuration Options
Programming Guide for DMA Controller
Startup
Example: Start-up Controller
Execute a DMA Transfer
Interrupt Service Routine
Example: IRQ Interrupt Service Routine
Example: IRQ_ABORT Interrupt Service Routine
Register Overview
Programming Guide for DMA Engine
Write Microcode to Program CCRx for AXI Transactions
Memory-to-Memory Transfers
PL Peripheral DMA Transfer Length Management
Example: Length Managed by Peripheral
Example: Length Managed by DMAC
Restart Channel using an Event
DMAC Executes DMAWFE before DMASEV
DMAC Executes DMASEV before DMAWFE
Interrupting a Processor
Instruction Set Reference
Programming Restrictions
Updating Channel Control Registers During a DMA Cycle
Updates That Affect the Destination Address
Updates That Affect the Source Address
Resource Sharing Between DMA Channels
System Functions
Clocks
Example: Enable Clocks
Peripheral Request Interface Clock
Resets
Controller Reset
PL Peripheral Reset
Reset Configuration of Controller
I/O Interface
AXI Master Interface
Peripheral Request Interface
DDR Memory Controller
Introduction
Features
DDR Controller System Interface (DDRI)
DDR Controller PHY (DDRP)
DDR Controller Core and Transaction Scheduler (DDRC)
Block Diagram
Notices
7z007s and 7z010 CLG225 Devices
Interconnect
DDR Memory Types, Densities, and Data Widths
I/O Signals
AXI Memory Port Interface (DDRI)
Introduction
Block Diagram
AXI Feature Support and Limitations
TrustZone
DDR Core and Transaction Scheduler (DDRC)
Row/Bank/Column Address Mapping
DDRC Arbitration
Priority, Aging Counter and Urgent Signals
Page-Match
Aging Counter
Stage 1 – AXI Port Arbitration
Stage 2 – Read Versus Write
High Priority Read Ports
Stage 3 – Transaction State
Read Priority Management
Write Combine
Credit Mechanism
Controller PHY (DDRP)
Functional Programming Model
Clock Operating Frequencies
DDR IOB Impedance Calibration
Calibration
DDR IOB Configuration
Configuration
VREF Configuration
DDR Controller Register Programming
DRAM Reset and Initialization
DDR Initialization Sequence
LPDDR2 Initialization Sequence
DDR2 Initialization Sequence
DDR3 Initialization Sequence
DRAM Input Impedance (ODT) Calibration
Calibration
DRAM Output Impedance (R ON ) Calibration
Calibration
DRAM Training
Write Leveling
Read DQS Gate Training
Read Data Eye Training
Write Data Eye Adjustment
Alternatives to Automatic DRAM Training
Automatic Training
Semi-Automatic Training
Multi-Set Semi-Automatic Training
Manual Training
DRAM Write Latency Restriction
Register Overview
DDRI
DDRC
DDRP
Error Correction Code (ECC)
ECC Initialization
ECC Error Behavior
Data Mask During ECC Mode
ECC Programming Model
Enabling ECC operation (Switching from Non-ECC Mode to ECC Mode)
Disabling the ECC Operation (Switching from ECC Mode to Non-ECC Mode)
Monitoring ECC Status
Operational Programming Model
Operating Modes
Changing Clock Frequencies
Power Down
Deep Power Down
Self Refresh
DDR Power Reduction
Clock Stop
Precharge Power Down
Self Refresh
Self Refresh Sequence
Static Memory Controller
Introduction
Features
NAND Flash Interface
Parallel (SRAM/NOR) Interface
Block Diagram
Interconnect Interfaces
Memory Manager
Format
Notices
7z007s and 7z010 CLG225 Devices
MIO Pin Options
Functional Operation
Boot Device
Clocks
Resets
ECC Support
Interrupts
PL353 Functionality
Address Map
I/O Signals
Optional Pins
Wiring Diagrams
Register Overview
Programming Model
NOR Flash Bandwidth
Quad-SPI Flash Controller
Introduction
Features
System Viewpoint
Address Map and Device Matching for Linear Address Mode
Block Diagram
Notices
Operating Restrictions
Functional Description
Operational Modes
I/O Mode
Flow Control
I/O Mode Transmit Registers (TXD)
FI F O R e a d s an d W ri t e s
I/O Mode Considerations
Linear Addressing Mode
AXI Interface Operation
AXI Read Command Processing
Interface Configuration and Read Modes
Performance Modes
Read Data Management
Read Latency
Unsupported Devices
Supported Memory Read and Write Commands
Programming Guide
Example: Start-up Sequence
Configuration
Example: Configure Controller
Linear Addressing Mode
Example: Linear Addressing Mode (Memory Reads)
Configure I/O Mode
Example: I/O Mode (Memory Reads and Writes)
Example: I/O Mode Interrupt Service Routine
I/O Mode Interrupts
Example: Interrupt Handler for Rx and Tx
Rx/Tx FIFO Response to I/O Command Sequences
Example: Write Enable Command (code 0x06 )
Example: Read Status Command (code 0x05 )
Example: Read Data Sequence
Register Overview
System Functions
Clocks
CPU_1x Clock
QSPI_REF_CLK and Quad-SPI Interface Clocks
Clock Ratio Restriction
Example: Setup Reference Clock
Quad-SPI Feedback Clock
Resets
Example: Reset the APB Interface and Quad-SPI Controller
I/O Interface
Wiring Connections
Single SS, 4-bit I/O
Dual SS, 8-bit Parallel
Dual SS, 4-bit Stacked I/O
Single SS, Legacy I/O
MIO Programming
Example: Program I/O for a Single Device
Option: Add Second Device Chip Select
Option: Add Second Serial Clock
Option: Add 4-bit Data
Option: Add Feedback Output Clock
MIO Signals
SD/SDIO Controller
Introduction
Key Features
System Viewpoint
Functional Description
AHB Interface and Interrupt Controller
SD/SDIO Host Controller
Data FIFO
Command and Control Logic
Bus Monitor
Stream Write and Read
Clocks
Soft Resets
FIFO Overrun and Underrun Conditions
Write
Read
Limitation
Programming Model
Data Transfer Protocol Overview
Single Block Transfer
Multiple Block Transfer
Infinite Block Transfer
Data Transfers Without DMA
Using DMA
Using ADMA
Abort Transaction
Synchronous Abort
External Interface Usage Example
Supported Configurations
Bus Voltage Translation
SDIO Controller Media Interface Signals
SDIO EMIO Considerations
General Purpose I/O (GPIO)
Introduction
Features
Block Diagram
Notices
7z007s and 7z010 CLG225 Devices
MIO Considerations
Functional Description
GPIO Control of Device Pins
EMIO Signals
Bank0, Bits[8:7] are Outputs
Interrupt Function
Limitation
Programming Guide
Start-up Sequence
Main Example: Start-up Sequence
GPIO Pin Configurations
Example: Configure MIO pin 10 as an output
Example: Configure MIO pin 10 as an input
Writing Data to GPIO Output Pins
Reading Data from GPIO Input Pins
GPIO as Wake-up Event
Register Overview
System Functions
Clocks
Resets
Interrupts
I/O Interface
MIO Programming
Example: Configure MIO pin 6 as a GPIO signal
USB Host, Device, and OTG Controller
Introduction
Features
Operating Modes
Hardware System Viewpoint
System Interfaces
ULPI I/O signals
I/O Wiring
Controller Block Diagram
The controller interfaces to the PS system memory on one side and an external ULPI PHY device on the USB side. A block diagram is shown in This Figure . A detailed functional block is shown in section Notices .
System Memory
DMA, Protocol Engines, Context and FIFOs
Port Transceiver Controller
ULPI Link Wrapper
ULPI Rx/Tx Commands
ULPI PHY Viewport
Programmable Timers
Software Programming Interface
Control and Status Registers
Clocks
Resets
Configuration, Control and Status
Data Structures
Device Mode
Host Mode
Link-list Concept
Implementation Summary
Documentation
Scope of TRM
Documents and Specifications
Zynq 7000 SoC Documents
7-Series FPGA Documents
USB Specifications
Chapter Nomenclature
Notices
7z007s and 7z010 CLG225 Devices
Chapter Overview
Functional Descriptions and Programming Guides
Functional Description
Controller Flow Diagram
DMA Engine
Data Transfers
Protocol Engine
Protocol Engine Functions
Port Controller
ULPI Link Wrapper
General Purpose Timers
Programming Overview and Reference
Limitation
Hardware/Software System
Operational Mode Control
States
Power Management
Stop-Clock
Suspend and Resume
Register Overview
The controller and all registers are reset by the assertion of the USB Ref Reset from the PS. The mechanism is described in Reset System . The reset value of the controller registers are shown in Appendix B. Software can reset the controller and the non-OTG registers by writing a 1 to the usb.USBCMD [RST] bit. The registers that are reset by usb.USBCMD [RST] are identified in a the last column of Table: USB Controller Register Overview .
Register Overview Table
Interrupt and Status Bits Overview
USBSTS Interrupt, Status and Enable Registers
OTG Status/Interrupt and Control Register
Device Mode Control
Controller State
USB Bus Reset Response
DCD Actions
Device Controller Reset
Port Change Detect
Device Endpoint Data Structures
Link-list Endpoint Descriptors
Descriptor and Data Flow
Manage Endpoints
Endpoint Registers
Endpoint Registers
Endpoint Configuration Registers
Endpoint Initialization
Stall
Data Toggle
Data Toggle Inhibit
Device Endpoint Packet Operational Model
Prime and Flush Endpoints
Prime Transmit Endpoints
Prime Receive Endpoints
Interrupt and Bulk Endpoint Operational Model
dQH.ZLT = 0, the default value
Tx dTD Completes
Rx dTD Completes
Interrupt and Bulk Endpoint Bus Response
Isochronous Endpoint Operational Model
Tx Isochronous Packet Retired
Rx Isochronous Packet Retired
Isochronous Pipe Synchronization
Isochronous Endpoint Bus Response
Control Endpoint Operational Model
Lockout and Tripwire for Setup Packets
Setup Packet Handling using the Tripwire
Example: Setup Packet Handing using the Tripwire
Data Phase
Status Phase
Control Endpoint Bus Response
Device Endpoint Descriptor Reference
Endpoint Queue Head Descriptor (dQH)
Endpoint Transfer Descriptor (dTD)
Endpoint Transfer Overlay Area
Transfer Overlay Table
Multiplier Override (MultO) Bit Field
Example 1: Send three packets
Example 2: Send two packets
Buffer Pointer Pages
The buffer pointers are aligned to 4KB boundaries. The total byes and buffer pointers are discussed in section Total Bytes to Transfer Parameter .
Total Bytes to Transfer Parameter
The maximum value that the DCD may store in the field is 5 times 4 KB (5000h). This is the maximum number of bytes that 5 page pointers can reference. Although it is possible to create a transfer up to 20 KB this assumes the 1st offset into the first page is 0. When the offset cannot be predetermined, crossing past the 5th page can be guaranteed by limiting the total bytes to 16 KB. Therefore, the maximum recommended transfer is 16 KB (4000h)
.Device Mode Note
Programming Guide for Device Controller
Software Model
USB Reset
Register Controlled Reset
Programming Guide for Device Endpoint Data Structures
Device Controller Initialization Overview
Manage Transfer Descriptors
Example: Initialize dQH
Example: Operational Model for Setup Transfers
Manage Transfers with Transfer Descriptors
Example: Build a Transfer Descriptor
Example: Execute a Transfer Descriptor
Transfer Completion
Example: Flushing/De-priming an Endpoint
Device Errors
Service Device Mode Interrupts
High-Frequency Interrupts
Low-Frequency Interrupts
Error Interrupts
Host Mode Data Structures
EHCI Enhancements and Deviations
Transfer Schedules
Suspend and Resume
Host Controller Transfer Schedule Structures
Interrupt, Control, and Bulk data streams are managed via queue heads (QH) and queue element transfer descriptors (qTD). These data structures are optimized to reduce the total memory footprint of the schedule and to reduce (on average) the number of memory accesses needed to execute a USB transaction.
Periodic Schedule
Periodic Frame List
Asynchronous Schedule
EHCI Implementation
Overview
Embedded Transaction Translator
EHCI Reserved Bits
No PCI Bus Registers
SOF Interrupt
Capability Register Bit Fields Added
Operational Register and Bit Field Added
Embedded Transaction Translator
Functional Block Diagram
EHCI Functional Changes for the TT
Port Reset Timer Enhancement
Example: Port Reset Timer for Discovery
Port Speed Detection Mechanism
FS/LS Data Structures
Operational Model of the TT
Microframe Pipeline
Split Transfer State Machines
Asynchronous Transaction Scheduling and Buffer Management
Periodic Transaction Scheduling and Buffer Management
Port Test Mode
Host Data Structures Reference
Section Content
Descriptor Usage
Transfer Descriptor Type (TYP) Field
Isochronous (High Speed) Transfer Descriptor (iTD)
iTD DWord 0: Next Link Pointer
iTD DWords 1 to 8: Transaction Status and Control List
iTD DWords 9 to 15: Buffer Page Pointer List
Split Transaction Isochronous Transfer Descriptor (siTD)
siTD DWord 0: Next Link Pointer
siTD DWords 1 and 2: Endpoint Capabilities and Characteristics
Microframe C-mask
Microframe S-mask
siTD DWord 3: Transfer Status and Control
Status bits [7:0]
siTD DWords 4 and 5: Buffer Pointer List
siTD DWord 6: Back Link Pointer
Queue Element Transfer Descriptor (qTD)
qTD DWord 0: Next Pointer
qTD DWord 1: Alternate Next Element Pointer
qTD DWord 2: Token
qTD DWord 3 to 7: Buffer page Pointer List
Queue Head (QH)
QH Horizontal Link Pointer, DWord 0
QH DWords 1 and 2: Endpoint Capabilities and Characteristics
uFrame C-Mask
uFrame S-mask
QH DWord 3: Current qTD Pointer
Transfer Overlay Area
Periodic Frame Span Traversal Node (FSTN)
FSTN DWord 0: Normal Path Pointer
FSTN DWord 1: Back Path Link Pointer
Programming Guide for Host Controller
Controller Reset
Run/Stop
OTG Description and Reference
Hardware Assistance Features
Auto-Reset Option
Data-Pulse
B-Disconnect to A-Connect
OTG Interrupt and Control Bits
System Functions
Clocks
CPU_1x Clock
60 MHz PHY Clock
Reset Types
Controller Resets
OTG Mode Auto-Reset ULPI PHY Reset
USB Bus Reset
Summary of Resets
System Interrupt
APB Slave Interface
AHB Master Interface
The 32-bit AHB master interface is used by the DMA controller to read and write data packets and transfer descriptors. The interface is AMBA 3.0 compatible.
Unused Signals
I/O Interfaces
Wiring Connections
MIO-EMIO Programming
MIO Pins
Example: Program I/O for Controller 1
. MIO-EMIO Signals
Gigabit Ethernet Controller
Introduction
Block Diagram
Features
System Viewpoint
Clock Domains
Notices
7z007s and 7z010 CLG225 Devices
Jumbo Frames
Half Duplex
Application Notes
Functional Description and Programming Model
10/100/1000 Operation
MDIO Interface
MAC Transmitter
MAC Receiver
MAC Filtering
Broadcast Address
Hash Addressing
Copy All Frames (or Promiscuous Mode)
Disable Copy of Pause Frames
VLAN Support
Wake-on-LAN Support
DMA Block
Packet Buffer DMA
DMA Controller
Rx Buffers
Tx Buffers
DMA Bursting on the AHB
DMA Packet Buffer
Tx Packet Buffer
Rx Packet Buffer
Checksum Offloading
Rx Checksum Offload
Tx Checksum Offload
MAC 802.3 Pause Frame Support
802.3 Pause Frame Reception
802.3 Pause Frame Transmission
MAC PFC Priority Based Pause Frame Support
PFC Pause Frame Reception
PFC Pause Frame Transmission
Limitation
Programming Guide
Example: Programming Steps
Initialize the Controller
Configure the Controller
I/O Configuration
Gigabit Ethernet Controller using MIO
Example: Configuring Controllers for MIO
Gigabit Ethernet Controller using EMIO
Example: Configure Controllers for EMIO
Configure Clocks
Example: Configuring Clocks for MIO
Configure the PHY
Example: PHY Read/Write Operation
Example: PHY Initialization
Configure the Buffer Descriptors
Receive Buffer Descriptor List
Transmit Buffer Descriptor List
Configure Interrupts
Example: Configuring Interrupts
Enable the Controller
Transmitting Frames
Example: Transmitting a Frame
Receiving Frames
Example: Handling a Received Frame
Debug Guide
IEEE 1588 Timestamping
Register Overview
Control Registers
Status and Statistics Registers
Signals and I/O Connections
MIO–EMIO Interface Routing
Programmable Logic (PL) Implementations
RGMII Interface via MIO
GMII/MII Interface via EMIO
MDIO Interface Signals via MIO and EMIO
MIO Pin Considerations
Known Issues
SPI Controller
Introduction
Features
System Viewpoint
SPI Interface Controller
Clocking
MIO-EMIO
Block Diagram
APB Slave Interface
SPI Master Mode
SPI Slave Mode
Tx and Rx FIFOs
Notices
7z007s and 7z010 CLG225 Devices
Functional Description
Master Mode
Data Transfer
Auto/Manual SS and Start
Manual SS
Automatic SS
Manual Start
Enable
Command
Multi-Master Capability
Slave Mode
Clocking
Word Detection
FIFOs
RxFIFO
T xFIFO
FIFO Interrupts
Interrupt Register Bits, Logic Flow
SPI-to-SPI Connection
Limitation
Programming Guide
Start-up Sequence
Example: Start-up Sequence
Controller Configuration
Example: SPI 0 Configuration for Master Mode
Master Mode Data Transfer
Example: Master Mode – Manual SS and Manual Start
Example: Master Mode – Manual SS and Auto Start
Example: Master Mode – Auto SS and Manual Start
Slave Mode Data Transfer
Example: Slave Mode - Interrupt Driven
Interrupt Service Routine
Example: Interrupt Service Routine
Register Overview
System Functions
Resets
Example: Reset the APB Interface and SPI 0 Controller
Clocks
CPU_1x
SPI_Ref_Clk
Master Mode SCLK
Example: SCLK for Master Mode
Slave Mode SCLK
I/O Interfaces
Protocol
Master Mode
CLK_PH = 0
CLK_PH = 1
Back-to-Back Transfers
Slave Mode Requirements
MIO/EMIO Routing
Example: Program the I/O for SPI 0 on to MIO pins 16 to 21
Wiring Connections
Master Mode via MIO
Master Mode via EMIO
Slave Mode via MIO
MIO/EMIO Signal Tables
MIO Pin Limitation
EMIO Signals
CAN Controller
Introduction
Features
System Viewpoint
Block Diagram
Configuration Registers
Transmit and Receive Messages
Tx High Priority Buffer
Acceptance Filters
Notices
Restrictions
Functional Description
Controller Modes
Configuration Mode
Normal Mode
Sle e p Mode
Loop Back Mode (Diagno s tics)
Snoop Mode (Diagno s tics)
Mode Transitions
Mode Settings
Message Format
Bit Field Details
Writes
Reads
Message Buffering
Rx Messages
Tx Messages
Reads from RxFIFO
Rx and Tx Error Counters
Interrupts
List of Interrupts
RxFIFO and TxFIFO Interrupts
Example: Program RxFIFO Watermark Interrupt (12)
Example: Program TxFIFO Watermark Interrupt (13)
Example: Program TxFIFO Empty Interrupt (14)
Rx Message Filtering
Acceptance Filter Enable
Acceptance Filter Mask
Acceptance Filter Identifier
Example: Program Acceptance Filter
Program the AFMR and AFIR Registers
Example: Program the AFMR and AFIR for Standard Frames
Example: Program the AFMR and AFIR for Extended Frames
Protocol Engine
Rx/Tx Bit Timing Logic
Time Quanta Clock
Bitstream Processor
CAN0-to-CAN1 Connection
Limitation
Programming Guide
Overview
Configuration Mode State
Start-up Controller
Example: Start-up Sequence
Change Operating Mode
Example: Normal to Sleep Mode
Example: Configuration to Sleep Mode
Write Messages to TxFIFO
Example: Write Message to TxFIFO Using Polling Method
Example: Write Message to TxFIFO Using Interrupt Method
Write Messages to TxHPB
Example: Write Message to TxHPB
Read Messages from RxFIFO
Example: Read Message from RxFIFO Using Polling Method
Example: Read Message from RxFIFO Using Interrupt Method
Register Overview
System Functions
Clocks
CPU_1x Clock
Reference Clock
Example: Configure and Route Internal Clock for Reference Clock
Example: Source Controller Clock from MIO Pin
Resets
Example: Reset using Local CAN Reset
Example: Reset using Reset Subsystem
I/O Interface
MIO Programming
Example: Configure Rx/Tx Signals to MIO Pins
MIO-EMIO Signals
UART Controller
Introduction
Features
System Viewpoint
Notices
Reference Clock Operating Restrictions
7z007s and 7z010 CLG225 Devices
Functional Description
Block Diagram
Control Logic
Baud Rate Generator
Transmit FIFO
Transmitter Data Stream
Receiver FIFO
Receiver Data Capture
Receiver Parity Error
Receiver Framing Error
Receiver Overflow Error
Receiver Timeout Mechanism
I/O Mode Switch
Normal Mode
Automatic Echo Mode
Local Loopback Mode
Remote Loopback Mode
UART0-to-UART1 Connection
Status and Interrupts
Interrupt and Status Registers
Interrupt Mask Register
Channel Status
Non-FIFO Interrupts
FIFO Interrupts
Modem Control
Programmable Parameters
Example: Automatic Flow Control
Example: Manual Flow Control
Example: Monitor for a Change in the DCD DSR RI CTS Flow Control Signals
Limitation
Programming Guide
Start-up Sequence
Main Example: Start-up Sequence
Configure Controller Functions
Example: Configure Controller Functions
Transmit Data
Example: Transmit Data using the Polling Method
Example: Transmit Data using the Interrupt Method
Receive Data
Example: Receive Data using the Polling Method
Example: Receive Data using the Interrupt Method
RxFIFO Trigger Level Interrupt
Example: Set the RxFIFO Trigger Level and Enable the Interrupt
Register Overview
System Functions
Clocks
CPU_1x Clock
Reference Clock
Operating Restrictions
Example: Configure Reference Clock
Resets
Example: Controller Reset
I/O Interface
MIO Programming
Example: Route UART 0 RxD/TxD Signals to MIO Pins 46, 47
MIO – EMIO Signals
I2C Controller
Introduction
Features
System Block Diagram
Notices
7z007s and 7z010 CLG225 Devices
Functional Description
Block Diagram
Master Mode
Write Transfer
Read Transfer
Slave Monitor Mode
Slave Mode
Slave Transmitter
Slave Receiver
I2C Speed
Multi-Master Operation
I2C0-to-I2C1 Connection
Status and Interrupts
Interrupt Mask Register
Interrupt Status Register
Status Register
Limitation
Programmer’s Guide
Start-up Sequence
Controller Configuration
Example: Master Write Transfer
Configure Interrupts
Example: Program Example to Configure Completion Interrupt
Data Transfers
Example: Master Read Using Polled Method
Example: Master Write Using Polled Method
Example: Master Read Using Interrupt Method
Example: Master Write Using Interrupt Method
Example: Slave Monitor Mode
Register Overview
System Functions
Clocks
PS Clock Subsystem
CPU_1x Clock
Operating Restrictions
Reset Controller
Example: Controller Reset
I/O Interface
Pin Programming
Example: Route I2C 0 SCL and SDA Signals to MIO Pins 50, 51
MIO-EMIO Interfaces
Programmable Logic Description
Introduction
Features
PL Resources by Device Type
Notices
XADC Analog Mixed Signal Module (AMS)
Device Configuration (DevC)
PL Components
CLBs, Slices, and LUTs
Clock Management
Mixed-Mode Clock Manager and Phase-Locked Loop
MMCM Additional Programmable Features
Clock Distribution
Global Clock Lines
Regional Clocks
I/O Clocks
Block RAM
Synchronous Operation
Programmable Data Width
Error Detection and Correction
FIFO Controller
Digital Signal Processing — DSP Slice
Input/Output
PS-PL Interfaces
Voltage Level Shifters
SelectIO
I/O Electrical Characteristics
3-State Digitally Controlled Impedance and Low-Power I/O Features
I/O Logic
Input and Output Delay
ISERDES and OSERDES
GTX Low-Power Serial Transceivers
Transmitter
Receiver
Out-of-Band Signaling
Placement Information by Device/Package
XC7Z30-FBG484 Package Placement Diagram
XC7Z30-FBG676/FFG676 Package Placement Diagram
XC7Z30-SBG485 Package Placement Diagram
XC7Z35-FBG676/FFG676 and XC7Z45-FBG676/FFG676 Package Placement Diagrams
XC7Z35-FFG900, XC7Z45-FFG900, and XC7Z100-FFG900 Package Placement Diagram
XC7Z100-FFG1156 Package Placement Diagram
GTP Low-Power Serial Transceivers
Placement Information by Device/Package
XC7Z012-CLG485 and XC7Z015-CLG485 Package Placement Diagram
Integrated I/O Block for PCIe
Configuration
Programmable Logic Design Guide
Introduction
Programmable Logic for Software Offload
Benefits of Using PL to Implement Software Algorithms
Performance
Power
Latency
Designing PL Accelerators
Dataflow
PL Acceleration Limits
I/O Rate Limits
Resource Limits
Latency Limits
Power Offload
Real Time Offload
MicroBlaze Assisted Real Time Processing
PL Interrupt Servicing
HW State Machines
Reconfigurable Computing
Programmable Engines
PL and Memory System Performance Overview
Theoretical Bandwidth
DDR Efficiency
OCM Efficiency
Interconnect Throughput Bottlenecks
Choosing a Programmable Logic Interface
PL Interface Comparison Summary
Cortex-A9 CPU via General Purpose Masters
PS DMA Controller (DMAC) via General Purpose Masters
PL DMA via AXI High-Performance (HP) Interface
PL DMA via AXI ACP
PL DMA via General Purpose AXI Slave (GP)
Programmable Logic Test and Debug
Introduction
Features
Block Diagram
System Viewpoint
Functional Description
Basic Operation
Packet Generation
Typical Case – Trace Enabled, Cycle Count Enabled
No Cycle Count Case – Trace Enabled, Cycle Count Disabled
FIFO Overflow Case – Lost Trace
Synchronization Case
Packet Format
General Format
Trace Packet
Trigger Packet
Cycle Count Packet
FIFO Overflow Packet
First Packet After Enable
Synchronization Packet
Signals
General-Purpose Debug Signals
Trigger Signals
Trace Signals
Register Overview
Programming Model
FTM Security
Power Management
Introduction
Features
System Design Considerations
Device Technology Choice
PL Power-down Control
APU Maximum Frequency
DDR Memory Clock Frequency
DDR Memory Controller Modes and Configurations
Boot Interface Options
PS Clock Gating
Programming Guides
System Modules
Peripherals
Peripheral Clock Gating
I/O Buffers
Sleep Mode
Setup Wake-up Events
Programming Guide
Enter Sleep Mode
Exit Sleep Mode
Register Overview
Clocks
Introduction
System Block Diagram
Clock Generation
Three Programmable PLLs
Clock Branches
Reset
System Viewpoint
Power Management
Central Interconnect Clock Disable
CPU Clock
Ratio Examples
CPU Clock Divisor Restriction
Clock Usage
Interconnect Clock Domains
CPU Clock Stop
PS Peripheral AMBA Clocks
System Performance
System-wide Clock Frequency Examples
Clock Generator Design
PLL
Glitch-Free Clock Multiplexers
Glitch-Free Divider
Glitch-Free Clock Gate
Clock Select Multiplexers
DDR Clocks
IOP Module Clocks
USB Clocks
Ethernet Clocks
Ethernet Receiver Clocks
Ethernet Transmit Clocks
SDIO, SMC, SPI, Quad-SPI and UART Clocks
CAN Clocks
GPIO and I2C Clocks
PL Clocks
Clock Throttle
Clock Controller States
Clock Throttle Programming
Example: Stop/Start Clock
Example: Run the PL Clock for 592 Pulses and Stop
Example: Program 592 Pulses and Interact with the PL Trigger Input
Trace Port Clock
Register Overview
Programming Model
Branch Clock Generator
6-bit Programmable Divider
DDR Clocks
Digitally Controlled Impedance (DCI) Clock
PLLs
Enable PLL Mode when PLL Bypass Mode Pin is Tied High
Software-Controlled PLL Update
Reset System
Introduction
Features
Block Diagram
Reset Hierarchy
Boot Flow
Reset Sources
Power-on Reset (PS_POR_B)
External System Reset (PS_SRST_B)
System Software Reset
Watchdog Timer Resets
Secure Violation Lock Down
Debug Resets
Reset Effects
Peripherals
PL Resets
PL General Purpose User Resets
Register Overview
Persistent Registers
System Reset Control
Peripheral Reset Control
JTAG and DAP Subsystem
Introduction
Block Diagram
Features
Functional Description
I/O Signals
Programming Model
Use Case I: Software Debug with Trace Port Enabled
Use Case II: PS and PL Debug with Trace Port Enabled
Arm DAP Controller
Trace Port Interface Unit (TPIU)
AMD TAP Controller
System Test and Debug
Introduction
Features
Notices
7z007s and 7z010 CLG225 Devices
Functional Description
Debug Access Port (DAP)
Embedded Cross Trigger (ECT)
Program Trace Macrocell (PTM)
Instrumentation Trace Macrocell (ITM)
Funnel
Embedded Trace Buffer (ETB)
Trace Packet Output (TPIU)
I/O Signals
Register Overview
Memory Map
Functionality
Programming Model
Authentication Requirements
On-Chip Memory (OCM)
Introduction
Block Diagram
Features
System Viewpoint
Functional Description
Overview
Optimal Transfer Alignment
Clocking
Arbitration Scheme
Starvation Scenarios
Address Mapping
Mapping Summary
Initial View
OCM Relocation
SCU Address Filtering
Interrupts
Register Overview
Programming Model
Changing Address Mapping
AXI Responses
XADC Interface
Introduction
Control Interfaces
System Considerations
F e a tu re s
Analog-to-Digital Converters
PS-XADC I n t e r face
DRP Parallel Interface
PL-JTAG Interface
System Viewpoint
PS-XADC Interface
DRP Interface
PL JTAG Interface
Alarms
PS-XADC Interface Block Diag r am
Programming Guide
PS-XADC Interface
DRP Interface
PL-JTAG Interface
Notices
7z007s and 7z010 CLG225 Devices
Functional Description
Interface Arbiter (PL-JTAG and PS-XADC)
Serial Communication Channel (PL-JTAG and PS-XADC)
Analog-to-Digital Converter (All)
Sensor Alarms (PS-XADC and DRP)
PS-XADC Interface
DRP Interface
Functional Description
PS-XADC Interface Description
Serial Channel Clock Frequency
Command and Data Packets
PS-XADC Event Timing
Command Format
DPR Address and DRP Data
Read Data Format
Min/Max Voltage Thresholds
Critical Over-temperature Alarm
Programming Guide for the PS-XADC Interface
Example: Initialization of XADC via the PS-XADC Interface
Example: Start-up Sequence via the PS-XADC Interface
Read and Write to the FIFOs
Example: Write Command to the XADC
Example: Read the V CCPAUX value from the XADC
Interrupts
Example: Configure and Manage Alarm 5 (V CCPAUX )
Command Preparation
Example: Prepare Data for Writing to the XADC Register
Example: Prepare Data for Reading from the XADC Register
Register Overview
Programming Guide for the DRP Interface
Programming Guide for the PL-JTAG Interface
System Functions
Clocks
PS-XADC Interface Clocks
DRP Interface Clocks
PL-JTAG Interface Clocks
Resets
PS-XADC Interface Reset
XADC Reset
PCI Express
Introduction
Block Diagram
Features
Endpoint Use Case
Root Complex Use Case
Device Secure Boot
Introduction
Block Diagram
Features
Functional Description
Master Secure Boot
Power on Reset
RSA Authentication Performed on FSBL
Secure FSBL Decryption
Handoff to FSBL
External Boot Devices
Secure Boot Image.
Boot Image Header
Partition Data
RSA Authentication Certificate Format
eFUSE Settings
PL eFUSE Settings
PS eFUSE Settings
RSA Authentication
Boot Image and Bitstream Encryption
Boot Image and Bitstream Decryption and Authentication
HMAC Signature
AES Key Management
Secure Boot Features
Non-Secure Boot State
Secure Boot State
Security Lockdown
Boot Partition Search
JTAG and Debug Considerations
Readback
Secure Fallback Flow with eFUSE
Programming Considerations
Register Details
Overview
Acronyms
Module Summary
AXI_HP Interface (AFI) (axi_hp)
Register Summary
Register ( axi_hp ) AFI_RDCHAN_CTRL
Register AFI_RDCHAN_CTRL Details
Register ( axi_hp ) AFI_RDCHAN_ISSUINGCAP
Register AFI_RDCHAN_ISSUINGCAP Details
Register ( axi_hp ) AFI_RDQOS
Register AFI_RDQOS Details
Register ( axi_hp ) AFI_RDDATAFIFO_LEVEL
Register AFI_RDDATAFIFO_LEVEL Details
Register ( axi_hp ) AFI_RDDEBUG
Register AFI_RDDEBUG Details
Register ( axi_hp ) AFI_WRCHAN_CTRL
Register AFI_WRCHAN_CTRL Details
Register ( axi_hp ) AFI_WRCHAN_ISSUINGCAP
Register AFI_WRCHAN_ISSUINGCAP Details
Register ( axi_hp ) AFI_WRQOS
Register AFI_WRQOS Details
Register ( axi_hp ) AFI_WRDATAFIFO_LEVEL
Register AFI_WRDATAFIFO_LEVEL Details
Register ( axi_hp ) AFI_WRDEBUG
Register AFI_WRDEBUG Details
CAN Controller (can)
Register Summary
Register ( can ) XCANPS_SRR_OFFSET
Register XCANPS_SRR_OFFSET Details
Register ( can ) XCANPS_MSR_OFFSET
Register XCANPS_MSR_OFFSET Details
Register ( can ) XCANPS_BRPR_OFFSET
Register XCANPS_BRPR_OFFSET Details
Register ( can ) XCANPS_BTR_OFFSET
Register XCANPS_BTR_OFFSET Details
Register ( can ) XCANPS_ECR_OFFSET
Register XCANPS_ECR_OFFSET Details
Register ( can ) XCANPS_ESR_OFFSET
Register XCANPS_ESR_OFFSET Details
Register ( can ) XCANPS_SR_OFFSET
Register XCANPS_SR_OFFSET Details
Register ( can ) XCANPS_ISR_OFFSET
Register XCANPS_ISR_OFFSET Details
Register ( can ) XCANPS_IER_OFFSET
Register XCANPS_IER_OFFSET Details
Register ( can ) XCANPS_ICR_OFFSET
Register XCANPS_ICR_OFFSET Details
Register ( can ) XCANPS_TCR_OFFSET
Register XCANPS_TCR_OFFSET Details
Register ( can ) XCANPS_WIR_OFFSET
Register XCANPS_WIR_OFFSET Details
Register ( can ) XCANPS_TXFIFO_ID_OFFSET
Register XCANPS_TXFIFO_ID_OFFSET Details
Register ( can ) XCANPS_TXFIFO_DLC_OFFSET
Register XCANPS_TXFIFO_DLC_OFFSET Details
Register ( can ) XCANPS_TXFIFO_DW1_OFFSET
Register XCANPS_TXFIFO_DW1_OFFSET Details
Register ( can ) XCANPS_TXFIFO_DW2_OFFSET
Register XCANPS_TXFIFO_DW2_OFFSET Details
Register ( can ) XCANPS_TXHPB_ID_OFFSET
Register XCANPS_TXHPB_ID_OFFSET Details
Register ( can ) XCANPS_TXHPB_DLC_OFFSET
Register XCANPS_TXHPB_DLC_OFFSET Details
Register ( can ) XCANPS_TXHPB_DW1_OFFSET
Register XCANPS_TXHPB_DW1_OFFSET Details
Register ( can ) XCANPS_TXHPB_DW2_OFFSET
Register XCANPS_TXHPB_DW2_OFFSET Details
Register ( can ) XCANPS_RXFIFO_ID_OFFSET
Register XCANPS_RXFIFO_ID_OFFSET Details
Register ( can ) XCANPS_RXFIFO_DLC_OFFSET
Register XCANPS_RXFIFO_DLC_OFFSET Details
Register ( can ) XCANPS_RXFIFO_DW1_OFFSET
Register XCANPS_RXFIFO_DW1_OFFSET Details
Register ( can ) XCANPS_RXFIFO_DW2_OFFSET
Register XCANPS_RXFIFO_DW2_OFFSET Details
Register ( can ) XCANPS_AFR_OFFSET
Register XCANPS_AFR_OFFSET Details
Register ( can ) XCANPS_AFMR1_OFFSET
Register XCANPS_AFMR1_OFFSET Details
Register ( can ) XCANPS_AFIR1_OFFSET
Register XCANPS_AFIR1_OFFSET Details
Register ( can ) XCANPS_AFMR2_OFFSET
Register XCANPS_AFMR2_OFFSET Details
Register ( can ) XCANPS_AFIR2_OFFSET
Register XCANPS_AFIR2_OFFSET Details
Register ( can ) XCANPS_AFMR3_OFFSET
Register XCANPS_AFMR3_OFFSET Details
Register ( can ) XCANPS_AFIR3_OFFSET
Register XCANPS_AFIR3_OFFSET Details
Register ( can ) XCANPS_AFMR4_OFFSET
Register XCANPS_AFMR4_OFFSET Details
Register ( can ) XCANPS_AFIR4_OFFSET
Register XCANPS_AFIR4_OFFSET Details
DDR Memory Controller (ddrc)
Register Summary
Register ( ddrc ) ddrc_ctrl
Register ddrc_ctrl Details
Register ( ddrc ) Two_rank_cfg
Register Two_rank_cfg Details
Register ( ddrc ) HPR_reg
Register HPR_reg Details
Register ( ddrc ) LPR_reg
Register LPR_reg Details
Register ( ddrc ) WR_reg
Register WR_reg Details
Register ( ddrc ) DRAM_param_reg0
Register DRAM_param_reg0 Details
Register ( ddrc ) DRAM_param_reg1
Register DRAM_param_reg1 Details
Register ( ddrc ) DRAM_param_reg2
Register DRAM_param_reg2 Details
Register ( ddrc ) DRAM_param_reg3
Register DRAM_param_reg3 Details
Register ( ddrc ) DRAM_param_reg4
Register DRAM_param_reg4 Details
Register ( ddrc ) DRAM_init_param
Register DRAM_init_param Details
Register ( ddrc ) DRAM_EMR_reg
Register DRAM_EMR_reg Details
Register ( ddrc ) DRAM_EMR_MR_reg
Register DRAM_EMR_MR_reg Details
Register ( ddrc ) DRAM_burst8_rdwr
Register DRAM_burst8_rdwr Details
Register ( ddrc ) DRAM_disable_DQ
Register DRAM_disable_DQ Details
Register ( ddrc ) DRAM_addr_map_bank
Register DRAM_addr_map_bank Details
Register ( ddrc ) DRAM_addr_map_col
Register DRAM_addr_map_col Details
Register ( ddrc ) DRAM_addr_map_row
Register DRAM_addr_map_row Details
Register ( ddrc ) DRAM_ODT_reg
Register DRAM_ODT_reg Details
Register ( ddrc ) phy_dbg_reg
Register phy_dbg_reg Details
Register ( ddrc ) phy_cmd_timeout_rddata_cpt
Register phy_cmd_timeout_rddata_cpt Details
Register ( ddrc ) mode_sts_reg
Register mode_sts_reg Details
Register ( ddrc ) DLL_calib
Register DLL_calib Details
Register ( ddrc ) ODT_delay_hold
Register ODT_delay_hold Details
Register ( ddrc ) ctrl_reg1
Register ctrl_reg1 Details
Register ( ddrc ) ctrl_reg2
Register ctrl_reg2 Details
Register ( ddrc ) ctrl_reg3
Register ctrl_reg3 Details
Register ( ddrc ) ctrl_reg4
Register ctrl_reg4 Details
Register ( ddrc ) ctrl_reg5
Register ctrl_reg5 Details
Register ( ddrc ) ctrl_reg6
Register ctrl_reg6 Details
Register ( ddrc ) CHE_REFRESH_TIMER01
Register CHE_REFRESH_TIMER01 Details
Register ( ddrc ) CHE_T_ZQ
Register CHE_T_ZQ Details
Register ( ddrc ) CHE_T_ZQ_Short_Interval_Reg
Register CHE_T_ZQ_Short_Interval_Reg Details
Register ( ddrc ) deep_pwrdwn_reg
Register deep_pwrdwn_reg Details
Register ( ddrc ) reg_2c
Register reg_2c Details
Register ( ddrc ) reg_2d
Register reg_2d Details
Register ( ddrc ) dfi_timing
Register dfi_timing Details
Register ( ddrc ) CHE_ECC_CONTROL_REG_OFFSET
Register CHE_ECC_CONTROL_REG_OFFSET Details
Register ( ddrc ) CHE_CORR_ECC_LOG_REG_OFFSET
Register CHE_CORR_ECC_LOG_REG_OFFSET Details
Register ( ddrc ) CHE_CORR_ECC_ADDR_REG_OFFSET
Register CHE_CORR_ECC_ADDR_REG_OFFSET Details
Register ( ddrc ) CHE_CORR_ECC_DATA_31_0_REG_OFFSET
Register CHE_CORR_ECC_DATA_31_0_REG_OFFSET Details
Register ( ddrc ) CHE_CORR_ECC_DATA_63_32_REG_OFFSET
Register CHE_CORR_ECC_DATA_63_32_REG_OFFSET Details
Register ( ddrc ) CHE_CORR_ECC_DATA_71_64_REG_OFFSET
Register CHE_CORR_ECC_DATA_71_64_REG_OFFSET Details
Register ( ddrc ) CHE_UNCORR_ECC_LOG_REG_OFFSET
Register CHE_UNCORR_ECC_LOG_REG_OFFSET Details
Register ( ddrc ) CHE_UNCORR_ECC_ADDR_REG_OFFSET
Register CHE_UNCORR_ECC_ADDR_REG_OFFSET Details
Register ( ddrc ) CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET
Register CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET Details
Register ( ddrc ) CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET
Register CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET Details
Register ( ddrc ) CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET
Register CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET Details
Register ( ddrc ) CHE_ECC_STATS_REG_OFFSET
Register CHE_ECC_STATS_REG_OFFSET Details
Register ( ddrc ) ECC_scrub
Register ECC_scrub Details
Register ( ddrc ) CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET
Register CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET Details
Register ( ddrc ) CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET
Register CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET Details
Register ( ddrc ) phy_rcvr_enable
Register phy_rcvr_enable Details
Register ( ddrc ) PHY_Config0
Register PHY_Config0 to PHY_Config3 Details
Register ( ddrc ) phy_init_ratio0
Register phy_init_ratio0 to phy_init_ratio3 Details
Register ( ddrc ) phy_rd_dqs_cfg0
Register phy_rd_dqs_cfg0 to phy_rd_dqs_cfg3 Details
Register ( ddrc ) phy_wr_dqs_cfg0
Register phy_wr_dqs_cfg0 to phy_wr_dqs_cfg3 Details
Register ( ddrc ) phy_we_cfg0
Register phy_we_cfg0 to phy_we_cfg3 Details
Register ( ddrc ) wr_data_slv0
Register wr_data_slv0 to wr_data_slv3 Details
Register ( ddrc ) reg_64
Register reg_64 Details
Register ( ddrc ) reg_65
Register reg_65 Details
Register ( ddrc ) reg69_6a0
Register reg69_6a0 Details
Register ( ddrc ) reg69_6a1
Register reg69_6a1 Details
Register ( ddrc ) reg6c_6d2
Register reg6c_6d2 Details
Register ( ddrc ) reg6c_6d3
Register reg6c_6d3 Details
Register ( ddrc ) reg6e_710
Register reg6e_710 to reg6e_713 Details
Register ( ddrc ) phy_dll_sts0
Register phy_dll_sts0 to phy_dll_sts3 Details
Register ( ddrc ) dll_lock_sts
Register dll_lock_sts Details
Register ( ddrc ) phy_ctrl_sts
Register phy_ctrl_sts Details
Register ( ddrc ) phy_ctrl_sts_reg2
Register phy_ctrl_sts_reg2 Details
Register ( ddrc ) axi_id
Register axi_id Details
Register ( ddrc ) page_mask
Register page_mask Details
Register ( ddrc ) axi_priority_wr_port0
Register axi_priority_wr_port0 to axi_priority_wr_port3 Details
Register ( ddrc ) axi_priority_rd_port0
Register axi_priority_rd_port0 to axi_priority_rd_port3 Details
Register ( ddrc ) excl_access_cfg0
Register excl_access_cfg0 to excl_access_cfg3 Details
Register ( ddrc ) mode_reg_read
Register mode_reg_read Details
Register ( ddrc ) lpddr_ctrl0
Register lpddr_ctrl0 Details
Register ( ddrc ) lpddr_ctrl1
Register lpddr_ctrl1 Details
Register ( ddrc ) lpddr_ctrl2
Register lpddr_ctrl2 Details
Register ( ddrc ) lpddr_ctrl3
Register lpddr_ctrl3 Details
CoreSight Cross Trigger Interface (cti)
Register Summary
Register ( cti ) CTICONTROL
Register CTICONTROL Details
Register ( cti ) CTIINTACK
Register CTIINTACK Details
Register ( cti ) CTIAPPSET
Register CTIAPPSET Details
Register ( cti ) CTIAPPCLEAR
Register CTIAPPCLEAR Details
Register ( cti ) CTIAPPPULSE
Register CTIAPPPULSE Details
Register ( cti ) CTIINEN0
Register CTIINEN0 Details
Register ( cti ) CTIINEN1
Register CTIINEN1 Details
Register ( cti ) CTIINEN2
Register CTIINEN2 Details
Register ( cti ) CTIINEN3
Register CTIINEN3 Details
Register ( cti ) CTIINEN4
Register CTIINEN4 Details
Register ( cti ) CTIINEN5
Register CTIINEN5 Details
Register ( cti ) CTIINEN6
Register CTIINEN6 Details
Register ( cti ) CTIINEN7
Register CTIINEN7 Details
Register ( cti ) CTIOUTEN0
Register CTIOUTEN0 Details
Register ( cti ) CTIOUTEN1
Register CTIOUTEN1 Details
Register ( cti ) CTIOUTEN2
Register CTIOUTEN2 Details
Register ( cti ) CTIOUTEN3
Register CTIOUTEN3 Details
Register ( cti ) CTIOUTEN4
Register CTIOUTEN4 Details
Register ( cti ) CTIOUTEN5
Register CTIOUTEN5 Details
Register ( cti ) CTIOUTEN6
Register CTIOUTEN6 Details
Register ( cti ) CTIOUTEN7
Register CTIOUTEN7 Details
Register ( cti ) CTITRIGINSTATUS
Register CTITRIGINSTATUS Details
Register ( cti ) CTITRIGOUTSTATUS
Register CTITRIGOUTSTATUS Details
Register ( cti ) CTICHINSTATUS
Register CTICHINSTATUS Details
Register ( cti ) CTICHOUTSTATUS
Register CTICHOUTSTATUS Details
Register ( cti ) CTIGATE
Register CTIGATE Details
Register ( cti ) ASICCTL
Register ASICCTL Details
Register ( cti ) ITCHINACK
Register ITCHINACK Details
Register ( cti ) ITTRIGINACK
Register ITTRIGINACK Details
Register ( cti ) ITCHOUT
Register ITCHOUT Details
Register ( cti ) ITTRIGOUT
Register ITTRIGOUT Details
Register ( cti ) ITCHOUTACK
Register ITCHOUTACK Details
Register ( cti ) ITTRIGOUTACK
Register ITTRIGOUTACK Details
Register ( cti ) ITCHIN
Register ITCHIN Details
Register ( cti ) ITTRIGIN
Register ITTRIGIN Details
Register ( cti ) ITCTRL
Register ITCTRL Details
Register ( cti ) CTSR
Register CTSR Details
Register ( cti ) CTCR
Register CTCR Details
Register ( cti ) LAR
Register LAR Details
Register ( cti ) LSR
Register LSR Details
Register ( cti ) ASR
Register ASR Details
Register ( cti ) DEVID
Register DEVID Details
Register ( cti ) DTIR
Register DTIR Details
Register ( cti ) PERIPHID4
Register PERIPHID4 Details
Register ( cti ) PERIPHID5
Register PERIPHID5 Details
Register ( cti ) PERIPHID6
Register PERIPHID6 Details
Register ( cti ) PERIPHID7
Register PERIPHID7 Details
Register ( cti ) PERIPHID0
Register PERIPHID0 Details
Register ( cti ) PERIPHID1
Register PERIPHID1 Details
Register ( cti ) PERIPHID2
Register PERIPHID2 Details
Register ( cti ) PERIPHID3
Register PERIPHID3 Details
Register ( cti ) COMPID0
Register COMPID0 Details
Register ( cti ) COMPID1
Register COMPID1 Details
Register ( cti ) COMPID2
Register COMPID2 Details
Register ( cti ) COMPID3
Register COMPID3 Details
Performance Monitor Unit (cortexa9_pmu)
Register Summary
Register ( cortexa9_pmu ) PMXEVCNTR0
Register PMXEVCNTR0 Details
Register ( cortexa9_pmu ) PMXEVCNTR1
Register PMXEVCNTR1 Details
Register ( cortexa9_pmu ) PMXEVCNTR2
Register PMXEVCNTR2 Details
Register ( cortexa9_pmu ) PMXEVCNTR3
Register PMXEVCNTR3 Details
Register ( cortexa9_pmu ) PMXEVCNTR4
Register PMXEVCNTR4 Details
Register ( cortexa9_pmu ) PMXEVCNTR5
Register PMXEVCNTR5 Details
Register ( cortexa9_pmu ) PMCCNTR
Register PMCCNTR Details
Register ( cortexa9_pmu ) PMXEVTYPER0
Register PMXEVTYPER0 Details
Register ( cortexa9_pmu ) PMXEVTYPER1
Register PMXEVTYPER1 Details
Register ( cortexa9_pmu ) PMXEVTYPER2
Register PMXEVTYPER2 Details
Register ( cortexa9_pmu ) PMXEVTYPER3
Register PMXEVTYPER3 Details
Register ( cortexa9_pmu ) PMXEVTYPER4
Register PMXEVTYPER4 Details
Register ( cortexa9_pmu ) PMXEVTYPER5
Register PMXEVTYPER5 Details
Register ( cortexa9_pmu ) PMCNTENSET
Register PMCNTENSET Details
Register ( cortexa9_pmu ) PMCNTENCLR
Register PMCNTENCLR Details
Register ( cortexa9_pmu ) PMINTENSET
Register PMINTENSET Details
Register ( cortexa9_pmu ) PMINTENCLR
Register PMINTENCLR Details
Register ( cortexa9_pmu ) PMOVSR
Register PMOVSR Details
Register ( cortexa9_pmu ) PMSWINC
Register PMSWINC Details
Register ( cortexa9_pmu ) PMCR
Register PMCR Details
Register ( cortexa9_pmu ) PMUSERENR
Register PMUSERENR Details
CoreSight Program Trace Macrocell (ptm)
Register Summary
Register ( ptm ) ETMCR
Register ETMCR Details
Register ( ptm ) ETMCCR
Register ETMCCR Details
Register ( ptm ) ETMTRIGGER
Register ETMTRIGGER Details
Register ( ptm ) ETMSR
Register ETMSR Details
Register ( ptm ) ETMSCR
Register ETMSCR Details
Register ( ptm ) ETMTSSCR
Register ETMTSSCR Details
Register ( ptm ) ETMTEEVR
Register ETMTEEVR Details
Register ( ptm ) ETMTECR1
Register ETMTECR1 Details
Register ( ptm ) ETMACVR1
Register ETMACVR1 Details
Register ( ptm ) ETMACVR2
Register ETMACVR2 Details
Register ( ptm ) ETMACVR3
Register ETMACVR3 Details
Register ( ptm ) ETMACVR4
Register ETMACVR4 Details
Register ( ptm ) ETMACVR5
Register ETMACVR5 Details
Register ( ptm ) ETMACVR6
Register ETMACVR6 Details
Register ( ptm ) ETMACVR7
Register ETMACVR7 Details
Register ( ptm ) ETMACVR8
Register ETMACVR8 Details
Register ( ptm ) ETMACTR1
Register ETMACTR1 Details
Register ( ptm ) ETMACTR2
Register ETMACTR2 Details
Register ( ptm ) ETMACTR3
Register ETMACTR3 Details
Register ( ptm ) ETMACTR4
Register ETMACTR4 Details
Register ( ptm ) ETMACTR5
Register ETMACTR5 Details
Register ( ptm ) ETMACTR6
Register ETMACTR6 Details
Register ( ptm ) ETMACTR7
Register ETMACTR7 Details
Register ( ptm ) ETMACTR8
Register ETMACTR8 Details
Register ( ptm ) ETMCNTRLDVR1
Register ETMCNTRLDVR1 Details
Register ( ptm ) ETMCNTRLDVR2
Register ETMCNTRLDVR2 Details
Register ( ptm ) ETMCNTENR1
Register ETMCNTENR1 Details
Register ( ptm ) ETMCNTENR2
Register ETMCNTENR2 Details
Register ( ptm ) ETMCNTRLDEVR1
Register ETMCNTRLDEVR1 Details
Register ( ptm ) ETMCNTRLDEVR2
Register ETMCNTRLDEVR2 Details
Register ( ptm ) ETMCNTVR1
Register ETMCNTVR1 Details
Register ( ptm ) ETMCNTVR2
Register ETMCNTVR2 Details
Register ( ptm ) ETMSQ12EVR
Register ETMSQ12EVR Details
Register ( ptm ) ETMSQ21EVR
Register ETMSQ21EVR Details
Register ( ptm ) ETMSQ23EVR
Register ETMSQ23EVR Details
Register ( ptm ) ETMSQ31EVR
Register ETMSQ31EVR Details
Register ( ptm ) ETMSQ32EVR
Register ETMSQ32EVR Details
Register ( ptm ) ETMSQ13EVR
Register ETMSQ13EVR Details
Register ( ptm ) ETMSQR
Register ETMSQR Details
Register ( ptm ) ETMEXTOUTEVR1
Register ETMEXTOUTEVR1 Details
Register ( ptm ) ETMEXTOUTEVR2
Register ETMEXTOUTEVR2 Details
Register ( ptm ) ETMCIDCVR1
Register ETMCIDCVR1 Details
Register ( ptm ) ETMCIDCMR
Register ETMCIDCMR Details
Register ( ptm ) ETMSYNCFR
Register ETMSYNCFR Details
Register ( ptm ) ETMIDR
Register ETMIDR Details
Register ( ptm ) ETMCCER
Register ETMCCER Details
Register ( ptm ) ETMEXTINSELR
Register ETMEXTINSELR Details
Register ( ptm ) ETMTSEVR
Register ETMTSEVR Details
Register ( ptm ) ETMAUXCR
Register ETMAUXCR Details
Register ( ptm ) ETMTRACEIDR
Register ETMTRACEIDR Details
Register ( ptm ) OSLSR
Register OSLSR Details
Register ( ptm ) ETMPDSR
Register ETMPDSR Details
Register ( ptm ) ITMISCOUT
Register ITMISCOUT Details
Register ( ptm ) ITMISCIN
Register ITMISCIN Details
Register ( ptm ) ITTRIGGER
Register ITTRIGGER Details
Register ( ptm ) ITATBDATA0
Register ITATBDATA0 Details
Register ( ptm ) ITATBCTR2
Register ITATBCTR2 Details
Register ( ptm ) ITATBID
Register ITATBID Details
Register ( ptm ) ITATBCTR0
Register ITATBCTR0 Details
Register ( ptm ) ETMITCTRL
Register ETMITCTRL Details
Register ( ptm ) CTSR
Register CTSR Details
Register ( ptm ) CTCR
Register CTCR Details
Register ( ptm ) LAR
Register LAR Details
Register ( ptm ) LSR
Register LSR Details
Register ( ptm ) ASR
Register ASR Details
Register ( ptm ) DEVID
Register DEVID Details
Register ( ptm ) DTIR
Register DTIR Details
Register ( ptm ) PERIPHID4
Register PERIPHID4 Details
Register ( ptm ) PERIPHID5
Register PERIPHID5 Details
Register ( ptm ) PERIPHID6
Register PERIPHID6 Details
Register ( ptm ) PERIPHID7
Register PERIPHID7 Details
Register ( ptm ) PERIPHID0
Register PERIPHID0 Details
Register ( ptm ) PERIPHID1
Register PERIPHID1 Details
Register ( ptm ) PERIPHID2
Register PERIPHID2 Details
Register ( ptm ) PERIPHID3
Register PERIPHID3 Details
Register ( ptm ) COMPID0
Register COMPID0 Details
Register ( ptm ) COMPID1
Register COMPID1 Details
Register ( ptm ) COMPID2
Register COMPID2 Details
Register ( ptm ) COMPID3
Register COMPID3 Details
Debug Access Port (dap)
Register Summary
Register ( dap ) ROMENTRY00
Register ROMENTRY00 Details
Register ( dap ) ROMENTRY01
Register ROMENTRY01 Details
Register ( dap ) ROMENTRY02
Register ROMENTRY02 Details
Register ( dap ) ROMENTRY03
Register ROMENTRY03 Details
Register ( dap ) ROMENTRY04
Register ROMENTRY04 Details
Register ( dap ) ROMENTRY05
Register ROMENTRY05 Details
Register ( dap ) ROMENTRY06
Register ROMENTRY06 Details
Register ( dap ) ROMENTRY07
Register ROMENTRY07 Details
Register ( dap ) ROMENTRY08
Register ROMENTRY08 Details
Register ( dap ) ROMENTRY09
Register ROMENTRY09 Details
Register ( dap ) ROMENTRY10
Register ROMENTRY10 Details
Register ( dap ) ROMENTRY11
Register ROMENTRY11 Details
Register ( dap ) ROMENTRY12
Register ROMENTRY12 Details
Register ( dap ) ROMENTRY13
Register ROMENTRY13 Details
Register ( dap ) ROMENTRY14
Register ROMENTRY14 Details
Register ( dap ) ROMENTRY15
Register ROMENTRY15 Details
Register ( dap ) PERIPHID4
Register PERIPHID4 Details
Register ( dap ) PERIPHID5
Register PERIPHID5 Details
Register ( dap ) PERIPHID6
Register PERIPHID6 Details
Register ( dap ) PERIPHID7
Register PERIPHID7 Details
Register ( dap ) PERIPHID0
Register PERIPHID0 Details
Register ( dap ) PERIPHID1
Register PERIPHID1 Details
Register ( dap ) PERIPHID2
Register PERIPHID2 Details
Register ( dap ) PERIPHID3
Register PERIPHID3 Details
Register ( dap ) COMPID0
Register COMPID0 Details
Register ( dap ) COMPID1
Register COMPID1 Details
Register ( dap ) COMPID2
Register COMPID2 Details
Register ( dap ) COMPID3
Register COMPID3 Details
CoreSight Embedded Trace Buffer (etb)
Register Summary
Register ( etb ) RDP
Register RDP Details
Register ( etb ) STS
Register STS Details
Register ( etb ) RRD
Register RRD Details
Register ( etb ) RRP
Register RRP Details
Register ( etb ) RWP
Register RWP Details
Register ( etb ) TRG
Register TRG Details
Register ( etb ) CTL
Register CTL Details
Register ( etb ) RWD
Register RWD Details
Register ( etb ) FFSR
Register FFSR Details
Register ( etb ) FFCR
Register FFCR Details
Register ( etb ) ITMISCOP0
Register ITMISCOP0 Details
Register ( etb ) ITTRFLINACK
Register ITTRFLINACK Details
Register ( etb ) ITTRFLIN
Register ITTRFLIN Details
Register ( etb ) ITATBDATA0
Register ITATBDATA0 Details
Register ( etb ) ITATBCTR2
Register ITATBCTR2 Details
Register ( etb ) ITATBCTR1
Register ITATBCTR1 Details
Register ( etb ) ITATBCTR0
Register ITATBCTR0 Details
Register ( etb ) IMCR
Register IMCR Details
Register ( etb ) CTSR
Register CTSR Details
Register ( etb ) CTCR
Register CTCR Details
Register ( etb ) LAR
Register LAR Details
Register ( etb ) LSR
Register LSR Details
Register ( etb ) ASR
Register ASR Details
Register ( etb ) DEVID
Register DEVID Details
Register ( etb ) DTIR
Register DTIR Details
Register ( etb ) PERIPHID4
Register PERIPHID4 Details
Register ( etb ) PERIPHID5
Register PERIPHID5 Details
Register ( etb ) PERIPHID6
Register PERIPHID6 Details
Register ( etb ) PERIPHID7
Register PERIPHID7 Details
Register ( etb ) PERIPHID0
Register PERIPHID0 Details
Register ( etb ) PERIPHID1
Register PERIPHID1 Details
Register ( etb ) PERIPHID2
Register PERIPHID2 Details
Register ( etb ) PERIPHID3
Register PERIPHID3 Details
Register ( etb ) COMPID0
Register COMPID0 Details
Register ( etb ) COMPID1
Register COMPID1 Details
Register ( etb ) COMPID2
Register COMPID2 Details
Register ( etb ) COMPID3
Register COMPID3 Details
PL Fabric Trace Monitor (ftm)
Register Summary
Register ( ftm ) FTMGLBCTRL
Register FTMGLBCTRL Details
Register ( ftm ) FTMSTATUS
Register FTMSTATUS Details
Register ( ftm ) FTMCONTROL
Register FTMCONTROL Details
Register ( ftm ) FTMP2FDBG0
Register FTMP2FDBG0 Details
Register ( ftm ) FTMP2FDBG1
Register FTMP2FDBG1 Details
Register ( ftm ) FTMP2FDBG2
Register FTMP2FDBG2 Details
Register ( ftm ) FTMP2FDBG3
Register FTMP2FDBG3 Details
Register ( ftm ) FTMF2PDBG0
Register FTMF2PDBG0 Details
Register ( ftm ) FTMF2PDBG1
Register FTMF2PDBG1 Details
Register ( ftm ) FTMF2PDBG2
Register FTMF2PDBG2 Details
Register ( ftm ) FTMF2PDBG3
Register FTMF2PDBG3 Details
Register ( ftm ) CYCOUNTPRE
Register CYCOUNTPRE Details
Register ( ftm ) FTMSYNCRELOAD
Register FTMSYNCRELOAD Details
Register ( ftm ) FTMSYNCCOUT
Register FTMSYNCCOUT Details
Register ( ftm ) FTMATID
Register FTMATID Details
Register ( ftm ) FTMITTRIGOUTACK
Register FTMITTRIGOUTACK Details
Register ( ftm ) FTMITTRIGGER
Register FTMITTRIGGER Details
Register ( ftm ) FTMITTRACEDIS
Register FTMITTRACEDIS Details
Register ( ftm ) FTMITCYCCOUNT
Register FTMITCYCCOUNT Details
Register ( ftm ) FTMITATBDATA0
Register FTMITATBDATA0 Details
Register ( ftm ) FTMITATBCTR2
Register FTMITATBCTR2 Details
Register ( ftm ) FTMITATBCTR1
Register FTMITATBCTR1 Details
Register ( ftm ) FTMITATBCTR0
Register FTMITATBCTR0 Details
Register ( ftm ) FTMITCR
Register FTMITCR Details
Register ( ftm ) CLAIMTAGSET
Register CLAIMTAGSET Details
Register ( ftm ) CLAIMTAGCLR
Register CLAIMTAGCLR Details
Register ( ftm ) LOCK_ACCESS
Register LOCK_ACCESS Details
Register ( ftm ) LOCK_STATUS
Register LOCK_STATUS Details
Register ( ftm ) FTMAUTHSTATUS
Register FTMAUTHSTATUS Details
Register ( ftm ) FTMDEVID
Register FTMDEVID Details
Register ( ftm ) FTMDEV_TYPE
Register FTMDEV_TYPE Details
Register ( ftm ) FTMPERIPHID4
Register FTMPERIPHID4 Details
Register ( ftm ) FTMPERIPHID5
Register FTMPERIPHID5 Details
Register ( ftm ) FTMPERIPHID6
Register FTMPERIPHID6 Details
Register ( ftm ) FTMPERIPHID7
Register FTMPERIPHID7 Details
Register ( ftm ) FTMPERIPHID0
Register FTMPERIPHID0 Details
Register ( ftm ) FTMPERIPHID1
Register FTMPERIPHID1 Details
Register ( ftm ) FTMPERIPHID2
Register FTMPERIPHID2 Details
Register ( ftm ) FTMPERIPHID3
Register FTMPERIPHID3 Details
Register ( ftm ) FTMCOMPONID0
Register FTMCOMPONID0 Details
Register ( ftm ) FTMCOMPONID1
Register FTMCOMPONID1 Details
Register ( ftm ) FTMCOMPONID2
Register FTMCOMPONID2 Details
Register ( ftm ) FTMCOMPONID3
Register FTMCOMPONID3 Details
CoreSight Trace Funnel (funnel)
Register Summary
Register ( funnel ) Control
Register Control Details
Register ( funnel ) PriControl
Register PriControl Details
Register ( funnel ) ITATBDATA0
Register ITATBDATA0 Details
Register ( funnel ) ITATBCTR2
Register ITATBCTR2 Details
Register ( funnel ) ITATBCTR1
Register ITATBCTR1 Details
Register ( funnel ) ITATBCTR0
Register ITATBCTR0 Details
Register ( funnel ) IMCR
Register IMCR Details
Register ( funnel ) CTSR
Register CTSR Details
Register ( funnel ) CTCR
Register CTCR Details
Register ( funnel ) LAR
Register LAR Details
Register ( funnel ) LSR
Register LSR Details
Register ( funnel ) ASR
Register ASR Details
Register ( funnel ) DEVID
Register DEVID Details
Register ( funnel ) DTIR
Register DTIR Details
Register ( funnel ) PERIPHID4
Register PERIPHID4 Details
Register ( funnel ) PERIPHID5
Register PERIPHID5 Details
Register ( funnel ) PERIPHID6
Register PERIPHID6 Details
Register ( funnel ) PERIPHID7
Register PERIPHID7 Details
Register ( funnel ) PERIPHID0
Register PERIPHID0 Details
Register ( funnel ) PERIPHID1
Register PERIPHID1 Details
Register ( funnel ) PERIPHID2
Register PERIPHID2 Details
Register ( funnel ) PERIPHID3
Register PERIPHID3 Details
Register ( funnel ) COMPID0
Register COMPID0 Details
Register ( funnel ) COMPID1
Register COMPID1 Details
Register ( funnel ) COMPID2
Register COMPID2 Details
Register ( funnel ) COMPID3
Register COMPID3 Details
CoreSight Intstrumentation Trace Macrocell (itm)
Register Summary
Register ( itm ) StimPort00
Register StimPort00 Details
Register ( itm ) StimPort01
Register StimPort01 Details
Register ( itm ) StimPort02
Register StimPort02 Details
Register ( itm ) StimPort03
Register StimPort03 Details
Register ( itm ) StimPort04
Register StimPort04 Details
Register ( itm ) StimPort05
Register StimPort05 Details
Register ( itm ) StimPort06
Register StimPort06 Details
Register ( itm ) StimPort07
Register StimPort07 Details
Register ( itm ) StimPort08
Register StimPort08 Details
Register ( itm ) StimPort09
Register StimPort09 Details
Register ( itm ) StimPort10
Register StimPort10 Details
Register ( itm ) StimPort11
Register StimPort11 Details
Register ( itm ) StimPort12
Register StimPort12 Details
Register ( itm ) StimPort13
Register StimPort13 Details
Register ( itm ) StimPort14
Register StimPort14 Details
Register ( itm ) StimPort15
Register StimPort15 Details
Register ( itm ) StimPort16
Register StimPort16 Details
Register ( itm ) StimPort17
Register StimPort17 Details
Register ( itm ) StimPort18
Register StimPort18 Details
Register ( itm ) StimPort19
Register StimPort19 Details
Register ( itm ) StimPort20
Register StimPort20 Details
Register ( itm ) StimPort21
Register StimPort21 Details
Register ( itm ) StimPort22
Register StimPort22 Details
Register ( itm ) StimPort23
Register StimPort23 Details
Register ( itm ) StimPort24
Register StimPort24 Details
Register ( itm ) StimPort25
Register StimPort25 Details
Register ( itm ) StimPort26
Register StimPort26 Details
Register ( itm ) StimPort27
Register StimPort27 Details
Register ( itm ) StimPort28
Register StimPort28 Details
Register ( itm ) StimPort29
Register StimPort29 Details
Register ( itm ) StimPort30
Register StimPort30 Details
Register ( itm ) StimPort31
Register StimPort31 Details
Register ( itm ) TER
Register TER Details
Register ( itm ) TTR
Register TTR Details
Register ( itm ) CR
Register CR Details
Register ( itm ) SCR
Register SCR Details
Register ( itm ) ITTRIGOUTACK
Register ITTRIGOUTACK Details
Register ( itm ) ITTRIGOUT
Register ITTRIGOUT Details
Register ( itm ) ITATBDATA0
Register ITATBDATA0 Details
Register ( itm ) ITATBCTR2
Register ITATBCTR2 Details
Register ( itm ) ITATABCTR1
Register ITATABCTR1 Details
Register ( itm ) ITATBCTR0
Register ITATBCTR0 Details
Register ( itm ) IMCR
Register IMCR Details
Register ( itm ) CTSR
Register CTSR Details
Register ( itm ) CTCR
Register CTCR Details
Register ( itm ) LAR
Register LAR Details
Register ( itm ) LSR
Register LSR Details
Register ( itm ) ASR
Register ASR Details
Register ( itm ) DEVID
Register DEVID Details
Register ( itm ) DTIR
Register DTIR Details
Register ( itm ) PERIPHID4
Register PERIPHID4 Details
Register ( itm ) PERIPHID5
Register PERIPHID5 Details
Register ( itm ) PERIPHID6
Register PERIPHID6 Details
Register ( itm ) PERIPHID7
Register PERIPHID7 Details
Register ( itm ) PERIPHID0
Register PERIPHID0 Details
Register ( itm ) PERIPHID1
Register PERIPHID1 Details
Register ( itm ) PERIPHID2
Register PERIPHID2 Details
Register ( itm ) PERIPHID3
Register PERIPHID3 Details
Register ( itm ) COMPID0
Register COMPID0 Details
Register ( itm ) COMPID1
Register COMPID1 Details
Register ( itm ) COMPID2
Register COMPID2 Details
Register ( itm ) COMPID3
Register COMPID3 Details
CoreSight Trace Packet Output (tpiu)
Register Summary
Register ( tpiu ) SuppSize
Register SuppSize Details
Register ( tpiu ) CurrentSize
Register CurrentSize Details
Register ( tpiu ) SuppTrigMode
Register SuppTrigMode Details
Register ( tpiu ) TrigCount
Register TrigCount Details
Register ( tpiu ) TrigMult
Register TrigMult Details
Register ( tpiu ) SuppTest
Register SuppTest Details
Register ( tpiu ) CurrentTest
Register CurrentTest Details
Register ( tpiu ) TestRepeatCount
Register TestRepeatCount Details
Register ( tpiu ) FFSR
Register FFSR Details
Register ( tpiu ) FFCR
Register FFCR Details
Register ( tpiu ) FormatSyncCount
Register FormatSyncCount Details
Register ( tpiu ) EXTCTLIn
Register EXTCTLIn Details
Register ( tpiu ) EXTCTLOut
Register EXTCTLOut Details
Register ( tpiu ) ITTRFLINACK
Register ITTRFLINACK Details
Register ( tpiu ) ITTRFLIN
Register ITTRFLIN Details
Register ( tpiu ) ITATBDATA0
Register ITATBDATA0 Details
Register ( tpiu ) ITATBCTR2
Register ITATBCTR2 Details
Register ( tpiu ) ITATBCTR1
Register ITATBCTR1 Details
Register ( tpiu ) ITATBCTR0
Register ITATBCTR0 Details
Register ( tpiu ) IMCR
Register IMCR Details
Register ( tpiu ) CTSR
Register CTSR Details
Register ( tpiu ) CTCR
Register CTCR Details
Register ( tpiu ) LAR
Register LAR Details
Register ( tpiu ) LSR
Register LSR Details
Register ( tpiu ) ASR
Register ASR Details
Register ( tpiu ) DEVID
Register DEVID Details
Register ( tpiu ) DTIR
Register DTIR Details
Register ( tpiu ) PERIPHID4
Register PERIPHID4 Details
Register ( tpiu ) PERIPHID5
Register PERIPHID5 Details
Register ( tpiu ) PERIPHID6
Register PERIPHID6 Details
Register ( tpiu ) PERIPHID7
Register PERIPHID7 Details
Register ( tpiu ) PERIPHID0
Register PERIPHID0 Details
Register ( tpiu ) PERIPHID1
Register PERIPHID1 Details
Register ( tpiu ) PERIPHID2
Register PERIPHID2 Details
Register ( tpiu ) PERIPHID3
Register PERIPHID3 Details
Register ( tpiu ) COMPID0
Register COMPID0 Details
Register ( tpiu ) COMPID1
Register COMPID1 Details
Register ( tpiu ) COMPID2
Register COMPID2 Details
Register ( tpiu ) COMPID3
Register COMPID3 Details
Device Configuration Interface (devcfg)
Register Summary
Register ( devcfg ) XDCFG_CTRL_OFFSET
Register XDCFG_CTRL_OFFSET Details
Register ( devcfg ) XDCFG_LOCK_OFFSET
Register XDCFG_LOCK_OFFSET Details
Register ( devcfg ) XDCFG_CFG_OFFSET
Register XDCFG_CFG_OFFSET Details
Register ( devcfg ) XDCFG_INT_STS_OFFSET
Register XDCFG_INT_STS_OFFSET Details
Register ( devcfg ) XDCFG_INT_MASK_OFFSET
Register XDCFG_INT_MASK_OFFSET Details
Register ( devcfg ) XDCFG_STATUS_OFFSET
Register XDCFG_STATUS_OFFSET Details
Register ( devcfg ) XDCFG_DMA_SRC_ADDR_OFFSET
Register XDCFG_DMA_SRC_ADDR_OFFSET Details
Register ( devcfg ) XDCFG_DMA_DEST_ADDR_OFFSET
Register XDCFG_DMA_DEST_ADDR_OFFSET Details
Register ( devcfg ) XDCFG_DMA_SRC_LEN_OFFSET
Register XDCFG_DMA_SRC_LEN_OFFSET Details
Register ( devcfg ) XDCFG_DMA_DEST_LEN_OFFSET
Register XDCFG_DMA_DEST_LEN_OFFSET Details
Register ( devcfg ) XDCFG_MULTIBOOT_ADDR_OFFSET
Register XDCFG_MULTIBOOT_ADDR_OFFSET Details
Register ( devcfg ) XDCFG_UNLOCK_OFFSET
Register XDCFG_UNLOCK_OFFSET Details
Register ( devcfg ) XDCFG_MCTRL_OFFSET
Register XDCFG_MCTRL_OFFSET Details
Register ( devcfg ) XADCIF_CFG
Register XADCIF_CFG Details
Register ( devcfg ) XADCIF_INT_STS
Register XADCIF_INT_STS Details
Register ( devcfg ) XADCIF_INT_MASK
Register XADCIF_INT_MASK Details
Register ( devcfg ) XADCIF_MSTS
Register XADCIF_MSTS Details
Register ( devcfg ) XADCIF_CMDFIFO
Register XADCIF_CMDFIFO Details
Register ( devcfg ) XADCIF_RDFIFO
Register XADCIF_RDFIFO Details
Register ( devcfg ) XADCIF_MCTL
Register XADCIF_MCTL Details
DMA Controller (dmac)
Register Summary
Register ( dmac ) XDMAPS_DS_OFFSET
Register XDMAPS_DS_OFFSET Details
Register ( dmac ) XDMAPS_DPC_OFFSET
Register XDMAPS_DPC_OFFSET Details
Register ( dmac ) XDMAPS_INTEN_OFFSET
Register XDMAPS_INTEN_OFFSET Details
Register ( dmac ) XDMAPS_ES_OFFSET
Register XDMAPS_ES_OFFSET Details
Register ( dmac ) XDMAPS_INTSTATUS_OFFSET
Register XDMAPS_INTSTATUS_OFFSET Details
Register ( dmac ) XDMAPS_INTCLR_OFFSET
Register XDMAPS_INTCLR_OFFSET Details
Register ( dmac ) XDMAPS_FSM_OFFSET
Register XDMAPS_FSM_OFFSET Details
Register ( dmac ) XDMAPS_FSC_OFFSET
Register XDMAPS_FSC_OFFSET Details
Register ( dmac ) XDMAPS_FTM_OFFSET
Register XDMAPS_FTM_OFFSET Details
Register ( dmac ) XDMAPS_FTC0_OFFSET
Register XDMAPS_FTC0_OFFSET Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_1
Register XDmaPs_FTCn_OFFSET_1 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_2
Register XDmaPs_FTCn_OFFSET_2 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_3
Register XDmaPs_FTCn_OFFSET_3 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_4
Register XDmaPs_FTCn_OFFSET_4 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_5
Register XDmaPs_FTCn_OFFSET_5 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_6
Register XDmaPs_FTCn_OFFSET_6 Details
Register ( dmac ) XDmaPs_FTCn_OFFSET_7
Register XDmaPs_FTCn_OFFSET_7 Details
Register ( dmac ) XDMAPS_CS0_OFFSET
Register XDMAPS_CS0_OFFSET Details
Register ( dmac ) XDMAPS_CPC0_OFFSET
Register XDMAPS_CPC0_OFFSET Details
Register ( dmac ) XDmaPs_CSn_OFFSET_1
Register XDmaPs_CSn_OFFSET_1 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_1
Register XDmaPs_CPCn_OFFSET_1 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_2
Register XDmaPs_CSn_OFFSET_2 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_2
Register XDmaPs_CPCn_OFFSET_2 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_3
Register XDmaPs_CSn_OFFSET_3 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_3
Register XDmaPs_CPCn_OFFSET_3 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_4
Register XDmaPs_CSn_OFFSET_4 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_4
Register XDmaPs_CPCn_OFFSET_4 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_5
Register XDmaPs_CSn_OFFSET_5 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_5
Register XDmaPs_CPCn_OFFSET_5 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_6
Register XDmaPs_CSn_OFFSET_6 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_6
Register XDmaPs_CPCn_OFFSET_6 Details
Register ( dmac ) XDmaPs_CSn_OFFSET_7
Register XDmaPs_CSn_OFFSET_7 Details
Register ( dmac ) XDmaPs_CPCn_OFFSET_7
Register XDmaPs_CPCn_OFFSET_7 Details
Register ( dmac ) XDMAPS_SA_0_OFFSET
Register XDMAPS_SA_0_OFFSET Details
Register ( dmac ) XDMAPS_DA_0_OFFSET
Register XDMAPS_DA_0_OFFSET Details
Register ( dmac ) XDMAPS_CC_0_OFFSET
Register XDMAPS_CC_0_OFFSET Details
Register ( dmac ) XDMAPS_LC0_0_OFFSET
Register XDMAPS_LC0_0_OFFSET Details
Register ( dmac ) XDMAPS_LC1_0_OFFSET
Register XDMAPS_LC1_0_OFFSET Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_1
Register XDmaPs_SA_n_OFFSET_1 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_1
Register XDmaPs_DA_n_OFFSET_1 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_1
Register XDmaPs_CC_n_OFFSET_1 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_1
Register XDmaPs_LC0_n_OFFSET_1 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_1
Register XDmaPs_LC1_n_OFFSET_1 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_2
Register XDmaPs_SA_n_OFFSET_2 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_2
Register XDmaPs_DA_n_OFFSET_2 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_2
Register XDmaPs_CC_n_OFFSET_2 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_2
Register XDmaPs_LC0_n_OFFSET_2 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_2
Register XDmaPs_LC1_n_OFFSET_2 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_3
Register XDmaPs_SA_n_OFFSET_3 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_3
Register XDmaPs_DA_n_OFFSET_3 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_3
Register XDmaPs_CC_n_OFFSET_3 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_3
Register XDmaPs_LC0_n_OFFSET_3 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_3
Register XDmaPs_LC1_n_OFFSET_3 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_4
Register XDmaPs_SA_n_OFFSET_4 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_4
Register XDmaPs_DA_n_OFFSET_4 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_4
Register XDmaPs_CC_n_OFFSET_4 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_4
Register XDmaPs_LC0_n_OFFSET_4 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_4
Register XDmaPs_LC1_n_OFFSET_4 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_5
Register XDmaPs_SA_n_OFFSET_5 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_5
Register XDmaPs_DA_n_OFFSET_5 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_5
Register XDmaPs_CC_n_OFFSET_5 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_5
Register XDmaPs_LC0_n_OFFSET_5 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_5
Register XDmaPs_LC1_n_OFFSET_5 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_6
Register XDmaPs_SA_n_OFFSET_6 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_6
Register XDmaPs_DA_n_OFFSET_6 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_6
Register XDmaPs_CC_n_OFFSET_6 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_6
Register XDmaPs_LC0_n_OFFSET_6 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_6
Register XDmaPs_LC1_n_OFFSET_6 Details
Register ( dmac ) XDmaPs_SA_n_OFFSET_7
Register XDmaPs_SA_n_OFFSET_7 Details
Register ( dmac ) XDmaPs_DA_n_OFFSET_7
Register XDmaPs_DA_n_OFFSET_7 Details
Register ( dmac ) XDmaPs_CC_n_OFFSET_7
Register XDmaPs_CC_n_OFFSET_7 Details
Register ( dmac ) XDmaPs_LC0_n_OFFSET_7
Register XDmaPs_LC0_n_OFFSET_7 Details
Register ( dmac ) XDmaPs_LC1_n_OFFSET_7
Register XDmaPs_LC1_n_OFFSET_7 Details
Register ( dmac ) XDMAPS_DBGSTATUS_OFFSET
Register XDMAPS_DBGSTATUS_OFFSET Details
Register ( dmac ) XDMAPS_DBGCMD_OFFSET
Register XDMAPS_DBGCMD_OFFSET Details
Register ( dmac ) XDMAPS_DBGINST0_OFFSET
Register XDMAPS_DBGINST0_OFFSET Details
Register ( dmac ) XDMAPS_DBGINST1_OFFSET
Register XDMAPS_DBGINST1_OFFSET Details
Register ( dmac ) XDMAPS_CR0_OFFSET
Register XDMAPS_CR0_OFFSET Details
Register ( dmac ) XDMAPS_CR1_OFFSET
Register XDMAPS_CR1_OFFSET Details
Register ( dmac ) XDMAPS_CR2_OFFSET
Register XDMAPS_CR2_OFFSET Details
Register ( dmac ) XDMAPS_CR3_OFFSET
Register XDMAPS_CR3_OFFSET Details
Register ( dmac ) XDMAPS_CR4_OFFSET
Register XDMAPS_CR4_OFFSET Details
Register ( dmac ) XDMAPS_CRDN_OFFSET
Register XDMAPS_CRDN_OFFSET Details
Register ( dmac ) WD
Register WD Details
Register ( dmac ) XDMAPS_PERIPH_ID_0_OFFSET
Register XDMAPS_PERIPH_ID_0_OFFSET Details
Register ( dmac ) XDMAPS_PERIPH_ID_1_OFFSET
Register XDMAPS_PERIPH_ID_1_OFFSET Details
Register ( dmac ) XDMAPS_PERIPH_ID_2_OFFSET
Register XDMAPS_PERIPH_ID_2_OFFSET Details
Register ( dmac ) XDMAPS_PERIPH_ID_3_OFFSET
Register XDMAPS_PERIPH_ID_3_OFFSET Details
Register ( dmac ) XDMAPS_PCELL_ID_0_OFFSET
Register XDMAPS_PCELL_ID_0_OFFSET Details
Register ( dmac ) XDMAPS_PCELL_ID_1_OFFSET
Register XDMAPS_PCELL_ID_1_OFFSET Details
Register ( dmac ) XDMAPS_PCELL_ID_2_OFFSET
Register XDMAPS_PCELL_ID_2_OFFSET Details
Register ( dmac ) XDMAPS_PCELL_ID_3_OFFSET
Register XDMAPS_PCELL_ID_3_OFFSET Details
Gigabit Ethernet Controller (GEM)
Register Summary
Register ( GEM ) XEMACPS_NWCTRL_OFFSET
Register XEMACPS_NWCTRL_OFFSET Details
Register ( GEM ) XEMACPS_NWCFG_OFFSET
Register XEMACPS_NWCFG_OFFSET Details
Register ( GEM ) XEMACPS_NWSR_OFFSET
Register XEMACPS_NWSR_OFFSET Details
Register ( GEM ) XEMACPS_DMACR_OFFSET
Register XEMACPS_DMACR_OFFSET Details
Register ( GEM ) XEMACPS_TXSR_OFFSET
Register XEMACPS_TXSR_OFFSET Details
Register ( GEM ) XEMACPS_RXQBASE_OFFSET
Register XEMACPS_RXQBASE_OFFSET Details
Register ( GEM ) XEMACPS_TXQBASE_OFFSET
Register XEMACPS_TXQBASE_OFFSET Details
Register ( GEM ) XEMACPS_RXSR_OFFSET
Register XEMACPS_RXSR_OFFSET Details
Register ( GEM ) XEMACPS_ISR_OFFSET
Register XEMACPS_ISR_OFFSET Details
Register ( GEM ) XEMACPS_IER_OFFSET
Register XEMACPS_IER_OFFSET Details
Register ( GEM ) XEMACPS_IDR_OFFSET
Register XEMACPS_IDR_OFFSET Details
Register ( GEM ) XEMACPS_IMR_OFFSET
Register XEMACPS_IMR_OFFSET Details
Register ( GEM ) XEMACPS_PHYMNTNC_OFFSET
Register XEMACPS_PHYMNTNC_OFFSET Details
Register ( GEM ) XEMACPS_RXPAUSE_OFFSET
Register XEMACPS_RXPAUSE_OFFSET Details
Register ( GEM ) XEMACPS_TXPAUSE_OFFSET
Register XEMACPS_TXPAUSE_OFFSET Details
Register ( GEM ) XEMACPS_HASHL_OFFSET
Register XEMACPS_HASHL_OFFSET Details
Register ( GEM ) XEMACPS_HASHH_OFFSET
Register XEMACPS_HASHH_OFFSET Details
Register ( GEM ) XEMACPS_LADDR1L_OFFSET
Register XEMACPS_LADDR1L_OFFSET Details
Register ( GEM ) XEMACPS_LADDR1H_OFFSET
Register XEMACPS_LADDR1H_OFFSET Details
Register ( GEM ) XEMACPS_LADDR2L_OFFSET
Register XEMACPS_LADDR2L_OFFSET Details
Register ( GEM ) XEMACPS_LADDR2H_OFFSET
Register XEMACPS_LADDR2H_OFFSET Details
Register ( GEM ) XEMACPS_LADDR3L_OFFSET
Register XEMACPS_LADDR3L_OFFSET Details
Register ( GEM ) XEMACPS_LADDR3H_OFFSET
Register XEMACPS_LADDR3H_OFFSET Details
Register ( GEM ) XEMACPS_LADDR4L_OFFSET
Register XEMACPS_LADDR4L_OFFSET Details
Register ( GEM ) XEMACPS_LADDR4H_OFFSET
Register XEMACPS_LADDR4H_OFFSET Details
Register ( GEM ) XEMACPS_MATCH1_OFFSET
Register XEMACPS_MATCH1_OFFSET Details
Register ( GEM ) XEMACPS_MATCH2_OFFSET
Register XEMACPS_MATCH2_OFFSET Details
Register ( GEM ) XEMACPS_MATCH3_OFFSET
Register XEMACPS_MATCH3_OFFSET Details
Register ( GEM ) XEMACPS_MATCH4_OFFSET
Register XEMACPS_MATCH4_OFFSET Details
Register ( GEM ) wake_on_lan
Register wake_on_lan Details
Register ( GEM ) XEMACPS_STRETCH_OFFSET
Register XEMACPS_STRETCH_OFFSET Details
Register ( GEM ) stacked_vlan
Register stacked_vlan Details
Register ( GEM ) tx_pfc_pause
Register tx_pfc_pause Details
Register ( GEM ) spec_addr1_mask_bot
Register spec_addr1_mask_bot Details
Register ( GEM ) spec_addr1_mask_top
Register spec_addr1_mask_top Details
Register ( GEM ) module_id
Register module_id Details
Register ( GEM ) XEMACPS_OCTTXL_OFFSET
Register XEMACPS_OCTTXL_OFFSET Details
Register ( GEM ) XEMACPS_OCTTXH_OFFSET
Register XEMACPS_OCTTXH_OFFSET Details
Register ( GEM ) XEMACPS_TXCNT_OFFSET
Register XEMACPS_TXCNT_OFFSET Details
Register ( GEM ) XEMACPS_TXBCCNT_OFFSET
Register XEMACPS_TXBCCNT_OFFSET Details
Register ( GEM ) XEMACPS_TXMCCNT_OFFSET
Register XEMACPS_TXMCCNT_OFFSET Details
Register ( GEM ) XEMACPS_TXPAUSECNT_OFFSET
Register XEMACPS_TXPAUSECNT_OFFSET Details
Register ( GEM ) XEMACPS_TX64CNT_OFFSET
Register XEMACPS_TX64CNT_OFFSET Details
Register ( GEM ) XEMACPS_TX65CNT_OFFSET
Register XEMACPS_TX65CNT_OFFSET Details
Register ( GEM ) XEMACPS_TX128CNT_OFFSET
Register XEMACPS_TX128CNT_OFFSET Details
Register ( GEM ) XEMACPS_TX256CNT_OFFSET
Register XEMACPS_TX256CNT_OFFSET Details
Register ( GEM ) XEMACPS_TX512CNT_OFFSET
Register XEMACPS_TX512CNT_OFFSET Details
Register ( GEM ) XEMACPS_TX1024CNT_OFFSET
Register XEMACPS_TX1024CNT_OFFSET Details
Register ( GEM ) XEMACPS_TXURUNCNT_OFFSET
Register XEMACPS_TXURUNCNT_OFFSET Details
Register ( GEM ) XEMACPS_SNGLCOLLCNT_OFFSET
Register XEMACPS_SNGLCOLLCNT_OFFSET Details
Register ( GEM ) XEMACPS_MULTICOLLCNT_OFFSET
Register XEMACPS_MULTICOLLCNT_OFFSET Details
Register ( GEM ) XEMACPS_EXCESSCOLLCNT_OFFSET
Register XEMACPS_EXCESSCOLLCNT_OFFSET Details
Register ( GEM ) XEMACPS_LATECOLLCNT_OFFSET
Register XEMACPS_LATECOLLCNT_OFFSET Details
Register ( GEM ) XEMACPS_TXDEFERCNT_OFFSET
Register XEMACPS_TXDEFERCNT_OFFSET Details
Register ( GEM ) XEMACPS_TXCSENSECNT_OFFSET
Register XEMACPS_TXCSENSECNT_OFFSET Details
Register ( GEM ) XEMACPS_OCTRXL_OFFSET
Register XEMACPS_OCTRXL_OFFSET Details
Register ( GEM ) XEMACPS_OCTRXH_OFFSET
Register XEMACPS_OCTRXH_OFFSET Details
Register ( GEM ) XEMACPS_RXCNT_OFFSET
Register XEMACPS_RXCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXBROADCNT_OFFSET
Register XEMACPS_RXBROADCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXMULTICNT_OFFSET
Register XEMACPS_RXMULTICNT_OFFSET Details
Register ( GEM ) XEMACPS_RXPAUSECNT_OFFSET
Register XEMACPS_RXPAUSECNT_OFFSET Details
Register ( GEM ) XEMACPS_RX64CNT_OFFSET
Register XEMACPS_RX64CNT_OFFSET Details
Register ( GEM ) XEMACPS_RX65CNT_OFFSET
Register XEMACPS_RX65CNT_OFFSET Details
Register ( GEM ) XEMACPS_RX128CNT_OFFSET
Register XEMACPS_RX128CNT_OFFSET Details
Register ( GEM ) XEMACPS_RX256CNT_OFFSET
Register XEMACPS_RX256CNT_OFFSET Details
Register ( GEM ) XEMACPS_RX512CNT_OFFSET
Register XEMACPS_RX512CNT_OFFSET Details
Register ( GEM ) XEMACPS_RX1024CNT_OFFSET
Register XEMACPS_RX1024CNT_OFFSET Details
Register ( GEM ) XEMACPS_RXUNDRCNT_OFFSET
Register XEMACPS_RXUNDRCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXOVRCNT_OFFSET
Register XEMACPS_RXOVRCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXJABCNT_OFFSET
Register XEMACPS_RXJABCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXFCSCNT_OFFSET
Register XEMACPS_RXFCSCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXLENGTHCNT_OFFSET
Register XEMACPS_RXLENGTHCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXSYMBCNT_OFFSET
Register XEMACPS_RXSYMBCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXALIGNCNT_OFFSET
Register XEMACPS_RXALIGNCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXRESERRCNT_OFFSET
Register XEMACPS_RXRESERRCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXORCNT_OFFSET
Register XEMACPS_RXORCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXIPCCNT_OFFSET
Register XEMACPS_RXIPCCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXTCPCCNT_OFFSET
Register XEMACPS_RXTCPCCNT_OFFSET Details
Register ( GEM ) XEMACPS_RXUDPCCNT_OFFSET
Register XEMACPS_RXUDPCCNT_OFFSET Details
Register ( GEM ) XEMACPS_PTPP_RXNANOSEC_OFFSET
Register ( GEM ) design_cfg2
Register design_cfg2 Details
Register ( GEM ) design_cfg3
Register design_cfg3 Details
Register ( GEM ) design_cfg4
Register design_cfg4 Details
Register ( GEM ) design_cfg5
Register design_cfg5 Details
General Purpose I/O (gpio)
Register Summary
Register ( gpio ) XGPIOPS_DATA_LSW_OFFSET
Register XGPIOPS_DATA_LSW_OFFSET Details
Register ( gpio ) XGPIOPS_DATA_MSW_OFFSET
Register XGPIOPS_DATA_MSW_OFFSET Details
Register ( gpio ) MASK_DATA_1_LSW
Register MASK_DATA_1_LSW Details
Register ( gpio ) MASK_DATA_1_MSW
Register MASK_DATA_1_MSW Details
Register ( gpio ) MASK_DATA_2_LSW
Register MASK_DATA_2_LSW Details
Register ( gpio ) MASK_DATA_2_MSW
Register MASK_DATA_2_MSW Details
Register ( gpio ) MASK_DATA_3_LSW
Register MASK_DATA_3_LSW Details
Register ( gpio ) MASK_DATA_3_MSW
Register MASK_DATA_3_MSW Details
Register ( gpio ) XGPIOPS_DATA_OFFSET
Register XGPIOPS_DATA_OFFSET Details
Register ( gpio ) DATA_1
Register DATA_1 Details
Register ( gpio ) DATA_2
Register DATA_2 Details
Register ( gpio ) DATA_3
Register DATA_3 Details
Register ( gpio ) DATA_0_RO
Register DATA_0_RO Details
Register ( gpio ) DATA_1_RO
Register DATA_1_RO Details
Register ( gpio ) DATA_2_RO
Register DATA_2_RO Details
Register ( gpio ) DATA_3_RO
Register DATA_3_RO Details
Register ( gpio ) XGPIOPS_DIRM_OFFSET
Register XGPIOPS_DIRM_OFFSET Details
Register ( gpio ) XGPIOPS_OUTEN_OFFSET
Register XGPIOPS_OUTEN_OFFSET Details
Register ( gpio ) XGPIOPS_INTMASK_OFFSET
Register XGPIOPS_INTMASK_OFFSET Details
Register ( gpio ) XGPIOPS_INTEN_OFFSET
Register XGPIOPS_INTEN_OFFSET Details
Register ( gpio ) XGPIOPS_INTDIS_OFFSET
Register XGPIOPS_INTDIS_OFFSET Details
Register ( gpio ) XGPIOPS_INTSTS_OFFSET
Register XGPIOPS_INTSTS_OFFSET Details
Register ( gpio ) XGPIOPS_INTTYPE_OFFSET
Register XGPIOPS_INTTYPE_OFFSET Details
Register ( gpio ) XGPIOPS_INTPOL_OFFSET
Register XGPIOPS_INTPOL_OFFSET Details
Register ( gpio ) XGPIOPS_INTANY_OFFSET
Register XGPIOPS_INTANY_OFFSET Details
Register ( gpio ) DIRM_1
Register DIRM_1 Details
Register ( gpio ) OEN_1
Register OEN_1 Details
Register ( gpio ) INT_MASK_1
Register INT_MASK_1 Details
Register ( gpio ) INT_EN_1
Register INT_EN_1 Details
Register ( gpio ) INT_DIS_1
Register INT_DIS_1 Details
Register ( gpio ) INT_STAT_1
Register INT_STAT_1 Details
Register ( gpio ) INT_TYPE_1
Register INT_TYPE_1 Details
Register ( gpio ) INT_POLARITY_1
Register INT_POLARITY_1 Details
Register ( gpio ) INT_ANY_1
Register INT_ANY_1 Details
Register ( gpio ) DIRM_2
Register DIRM_2 Details
Register ( gpio ) OEN_2
Register OEN_2 Details
Register ( gpio ) INT_MASK_2
Register INT_MASK_2 Details
Register ( gpio ) INT_EN_2
Register INT_EN_2 Details
Register ( gpio ) INT_DIS_2
Register INT_DIS_2 Details
Register ( gpio ) INT_STAT_2
Register INT_STAT_2 Details
Register ( gpio ) INT_TYPE_2
Register INT_TYPE_2 Details
Register ( gpio ) INT_POLARITY_2
Register INT_POLARITY_2 Details
Register ( gpio ) INT_ANY_2
Register INT_ANY_2 Details
Register ( gpio ) DIRM_3
Register DIRM_3 Details
Register ( gpio ) OEN_3
Register OEN_3 Details
Register ( gpio ) INT_MASK_3
Register INT_MASK_3 Details
Register ( gpio ) INT_EN_3
Register INT_EN_3 Details
Register ( gpio ) INT_DIS_3
Register INT_DIS_3 Details
Register ( gpio ) INT_STAT_3
Register INT_STAT_3 Details
Register ( gpio ) INT_TYPE_3
Register INT_TYPE_3 Details
Register ( gpio ) INT_POLARITY_3
Register INT_POLARITY_3 Details
Register ( gpio ) INT_ANY_3
Register INT_ANY_3 Details
Interconnect QoS (qos301)
Register Summary
Register ( qos301 ) qos_cntl
Register qos_cntl Details
Register ( qos301 ) max_ot
Register max_ot Details
Register ( qos301 ) max_comb_ot
Register max_comb_ot Details
Register ( qos301 ) aw_p
Register aw_p Details
Register ( qos301 ) aw_b
Register aw_b Details
Register ( qos301 ) aw_r
Register aw_r Details
Register ( qos301 ) ar_p
Register ar_p Details
Register ( qos301 ) ar_b
Register ar_b Details
Register ( qos301 ) ar_r
Register ar_r Details
NIC301 Address Region Control (nic301_addr_region_ctrl_registers)
Register Summary
Register ( nic301_addr_region_ctrl_registers ) security_gp0_axi
Register security_gp0_axi Details
Register ( nic301_addr_region_ctrl_registers ) security_gp1_axi
Register security_gp1_axi Details
I2C Controller (IIC)
Register Summary
Register ( IIC ) XIICPS_CR_OFFSET
Register XIICPS_CR_OFFSET Details
Register ( IIC ) XIICPS_SR_OFFSET
Register XIICPS_SR_OFFSET Details
Register ( IIC ) XIICPS_ADDR_OFFSET
Register XIICPS_ADDR_OFFSET Details
Register ( IIC ) XIICPS_DATA_OFFSET
Register XIICPS_DATA_OFFSET Details
Register ( IIC ) XIICPS_ISR_OFFSET
Register XIICPS_ISR_OFFSET Details
Register ( IIC ) XIICPS_TRANS_SIZE_OFFSET
Register XIICPS_TRANS_SIZE_OFFSET Details
Register ( IIC ) XIICPS_SLV_PAUSE_OFFSET
Register XIICPS_SLV_PAUSE_OFFSET Details
Register ( IIC ) XIICPS_TIME_OUT_OFFSET
Register XIICPS_TIME_OUT_OFFSET Details
Register ( IIC ) XIICPS_IMR_OFFSET
Register XIICPS_IMR_OFFSET Details
Register ( IIC ) XIICPS_IER_OFFSET
Register XIICPS_IER_OFFSET Details
Register ( IIC ) XIICPS_IDR_OFFSET
Register XIICPS_IDR_OFFSET Details
L2 Cache (L2Cpl310)
Register Summary
Register ( L2Cpl310 ) reg0_cache_id
Register reg0_cache_id Details
Register ( L2Cpl310 ) reg0_cache_type
Register reg0_cache_type Details
Register ( L2Cpl310 ) reg1_control
Register reg1_control Details
Register ( L2Cpl310 ) reg1_aux_control
Register reg1_aux_control Details
Register ( L2Cpl310 ) reg1_tag_ram_control
Register reg1_tag_ram_control Details
Register ( L2Cpl310 ) reg1_data_ram_control
Register reg1_data_ram_control Details
Register ( L2Cpl310 ) reg2_ev_counter_ctrl
Register reg2_ev_counter_ctrl Details
Register ( L2Cpl310 ) reg2_ev_counter1_cfg
Register reg2_ev_counter1_cfg Details
Register ( L2Cpl310 ) reg2_ev_counter0_cfg
Register reg2_ev_counter0_cfg Details
Register ( L2Cpl310 ) reg2_ev_counter1
Register reg2_ev_counter1 Details
Register ( L2Cpl310 ) reg2_ev_counter0
Register reg2_ev_counter0 Details
Register ( L2Cpl310 ) reg2_int_mask
Register reg2_int_mask Details
Register ( L2Cpl310 ) reg2_int_mask_status
Register reg2_int_mask_status Details
Register ( L2Cpl310 ) reg2_int_raw_status
Register reg2_int_raw_status Details
Register ( L2Cpl310 ) reg2_int_clear
Register reg2_int_clear Details
Register ( L2Cpl310 ) reg7_cache_sync
Register reg7_cache_sync Details
Register ( L2Cpl310 ) reg7_inv_pa
Register reg7_inv_pa Details
Register ( L2Cpl310 ) reg7_inv_way
Register reg7_inv_way Details
Register ( L2Cpl310 ) reg7_clean_pa
Register reg7_clean_pa Details
Register ( L2Cpl310 ) reg7_clean_index
Register reg7_clean_index Details
Register ( L2Cpl310 ) reg7_clean_way
Register reg7_clean_way Details
Register ( L2Cpl310 ) reg7_clean_inv_pa
Register reg7_clean_inv_pa Details
Register ( L2Cpl310 ) reg7_clean_inv_index
Register reg7_clean_inv_index Details
Register ( L2Cpl310 ) reg7_clean_inv_way
Register reg7_clean_inv_way Details
Register ( L2Cpl310 ) reg9_d_lockdown0
Register reg9_d_lockdown0 Details
Register ( L2Cpl310 ) reg9_i_lockdown0
Register reg9_i_lockdown0 Details
Register ( L2Cpl310 ) reg9_d_lockdown1
Register reg9_d_lockdown1 Details
Register ( L2Cpl310 ) reg9_i_lockdown1
Register reg9_i_lockdown1 Details
Register ( L2Cpl310 ) reg9_d_lockdown2
Register reg9_d_lockdown2 Details
Register ( L2Cpl310 ) reg9_i_lockdown2
Register reg9_i_lockdown2 Details
Register ( L2Cpl310 ) reg9_d_lockdown3
Register reg9_d_lockdown3 Details
Register ( L2Cpl310 ) reg9_i_lockdown3
Register reg9_i_lockdown3 Details
Register ( L2Cpl310 ) reg9_d_lockdown4
Register reg9_d_lockdown4 Details
Register ( L2Cpl310 ) reg9_i_lockdown4
Register reg9_i_lockdown4 Details
Register ( L2Cpl310 ) reg9_d_lockdown5
Register reg9_d_lockdown5 Details
Register ( L2Cpl310 ) reg9_i_lockdown5
Register reg9_i_lockdown5 Details
Register ( L2Cpl310 ) reg9_d_lockdown6
Register reg9_d_lockdown6 Details
Register ( L2Cpl310 ) reg9_i_lockdown6
Register reg9_i_lockdown6 Details
Register ( L2Cpl310 ) reg9_d_lockdown7
Register reg9_d_lockdown7 Details
Register ( L2Cpl310 ) reg9_i_lockdown7
Register reg9_i_lockdown7 Details
Register ( L2Cpl310 ) reg9_lock_line_en
Register reg9_lock_line_en Details
Register ( L2Cpl310 ) reg9_unlock_way
Register reg9_unlock_way Details
Register ( L2Cpl310 ) reg12_addr_filtering_start
Register reg12_addr_filtering_start Details
Register ( L2Cpl310 ) reg12_addr_filtering_end
Register reg12_addr_filtering_end Details
Register ( L2Cpl310 ) reg15_debug_ctrl
Register reg15_debug_ctrl Details
Register ( L2Cpl310 ) reg15_prefetch_ctrl
Register reg15_prefetch_ctrl Details
Register ( L2Cpl310 ) reg15_power_ctrl
Register reg15_power_ctrl Details
Application Processing Unit (mpcore)
Register Summary
Register ( mpcore ) SCU_CONTROL_REGISTER
Register SCU_CONTROL_REGISTER Details
Register ( mpcore ) SCU_CONFIGURATION_REGISTER
Register SCU_CONFIGURATION_REGISTER Details
Register ( mpcore ) SCU_CPU_Power_Status_Register
Register SCU_CPU_Power_Status_Register Details
Register ( mpcore ) SCU_Invalidate_All_Registers_in_Secure_State
Register SCU_Invalidate_All_Registers_in_Secure_State Details
Register ( mpcore ) Filtering_Start_Address_Register
Register Filtering_Start_Address_Register Details
Register ( mpcore ) Filtering_End_Address_Register
Register Filtering_End_Address_Register Details
Register ( mpcore ) SCU_Access_Control_Register_SAC
Register SCU_Access_Control_Register_SAC Details
Register ( mpcore ) SCU_Non_secure_Access_Control_Register
Register SCU_Non_secure_Access_Control_Register Details
Register ( mpcore ) ICCICR
Register ICCICR Details
Register ( mpcore ) ICCPMR
Register ICCPMR Details
Register ( mpcore ) ICCBPR
Register ICCBPR Details
Register ( mpcore ) ICCIAR
Register ICCIAR Details
Register ( mpcore ) ICCEOIR
Register ICCEOIR Details
Register ( mpcore ) ICCRPR
Register ICCRPR Details
Register ( mpcore ) ICCHPIR
Register ICCHPIR Details
Register ( mpcore ) ICCABPR
Register ICCABPR Details
Register ( mpcore ) ICCIDR
Register ICCIDR Details
Register ( mpcore ) Global_Timer_Counter_Register0
Register Global_Timer_Counter_Register0 to Global_Timer_Counter_Register1 Details
Register ( mpcore ) Global_Timer_Control_Register
Register Global_Timer_Control_Register Details
Register ( mpcore ) Global_Timer_Interrupt_Status_Register
Register Global_Timer_Interrupt_Status_Register Details
Register ( mpcore ) Comparator_Value_Register0
Register Comparator_Value_Register0 to Comparator_Value_Register1 Details
Register ( mpcore ) Auto_increment_Register
Register Auto_increment_Register Details
Register ( mpcore ) Private_Timer_Load_Register
Register Private_Timer_Load_Register Details
Register ( mpcore ) Private_Timer_Counter_Register
Register Private_Timer_Counter_Register Details
Register ( mpcore ) Private_Timer_Control_Register
Register Private_Timer_Control_Register Details
Register ( mpcore ) Private_Timer_Interrupt_Status_Register
Register Private_Timer_Interrupt_Status_Register Details
Register ( mpcore ) Watchdog_Load_Register
Register Watchdog_Load_Register Details
Register ( mpcore ) Watchdog_Counter_Register
Register ( mpcore ) Watchdog_Control_Register
Register Watchdog_Control_Register Details
Register ( mpcore ) Watchdog_Interrupt_Status_Register
Register Watchdog_Interrupt_Status_Register Details
Register ( mpcore ) Watchdog_Reset_Status_Register
Register Watchdog_Reset_Status_Register Details
Register ( mpcore ) Watchdog_Disable_Register
Register Watchdog_Disable_Register Details
Register ( mpcore ) ICDDCR
Register ICDDCR Details
Register ( mpcore ) ICDICTR
Register ICDICTR Details
Register ( mpcore ) ICDIIDR
Register ICDIIDR Details
Register ( mpcore ) ICDISR0
Register ICDISR0 to ICDISR2 Details
Register ( mpcore ) ICDISER0
Register ICDISER0 Details
Register ( mpcore ) ICDISER1
Register ICDISER1 Details
Register ( mpcore ) ICDISER2
Register ICDISER2 Details
Register ( mpcore ) ICDICER0
Register ICDICER0 Details
Register ( mpcore ) ICDICER1
Register ICDICER1 Details
Register ( mpcore ) ICDICER2
Register ICDICER2 Details
Register ( mpcore ) ICDISPR0
Register ICDISPR0 to ICDISPR2 Details
Register ( mpcore ) ICDICPR0
Register ICDICPR0 to ICDICPR2 Details
Register ( mpcore ) ICDABR0
Register ICDABR0 to ICDABR2 Details
Register ( mpcore ) ICDIPR0
Register ICDIPR0 to ICDIPR23 Details
Register ( mpcore ) ICDIPTR0
Register ICDIPTR0 Details
Register ( mpcore ) ICDIPTR1
Register ICDIPTR1 Details
Register ( mpcore ) ICDIPTR2
Register ICDIPTR2 Details
Register ( mpcore ) ICDIPTR3
Register ICDIPTR3 Details
Register ( mpcore ) ICDIPTR4
Register ICDIPTR4 Details
Register ( mpcore ) ICDIPTR5
Register ICDIPTR5 Details
Register ( mpcore ) ICDIPTR6
Register ICDIPTR6 Details
Register ( mpcore ) ICDIPTR7
Register ICDIPTR7 Details
Register ( mpcore ) ICDIPTR8
Register ICDIPTR8 Details
Register ( mpcore ) ICDIPTR9
Register ICDIPTR9 Details
Register ( mpcore ) ICDIPTR10
Register ICDIPTR10 Details
Register ( mpcore ) ICDIPTR11
Register ICDIPTR11 Details
Register ( mpcore ) ICDIPTR12
Register ICDIPTR12 Details
Register ( mpcore ) ICDIPTR13
Register ICDIPTR13 Details
Register ( mpcore ) ICDIPTR14
Register ICDIPTR14 Details
Register ( mpcore ) ICDIPTR15
Register ICDIPTR15 Details
Register ( mpcore ) ICDIPTR16
Register ICDIPTR16 Details
Register ( mpcore ) ICDIPTR17
Register ICDIPTR17 Details
Register ( mpcore ) ICDIPTR18
Register ICDIPTR18 Details
Register ( mpcore ) ICDIPTR19
Register ICDIPTR19 Details
Register ( mpcore ) ICDIPTR20
Register ICDIPTR20 Details
Register ( mpcore ) ICDIPTR21
Register ICDIPTR21 Details
Register ( mpcore ) ICDIPTR22
Register ICDIPTR22 Details
Register ( mpcore ) ICDIPTR23
Register ICDIPTR23 Details
Register ( mpcore ) ICDICFR0
Register ICDICFR0 Details
Register ( mpcore ) ICDICFR1
Register ICDICFR1 Details
Register ( mpcore ) ICDICFR2
Register ICDICFR2 Details
Register ( mpcore ) ICDICFR3
Register ICDICFR3 Details
Register ( mpcore ) ICDICFR4
Register ICDICFR4 Details
Register ( mpcore ) ICDICFR5
Register ICDICFR5 Details
Register ( mpcore ) ppi_status
Register ppi_status Details
Register ( mpcore ) spi_status_0
Register spi_status_0 Details
Register ( mpcore ) spi_status_1
Register spi_status_1 Details
Register ( mpcore ) ICDSGIR
Register ICDSGIR Details
Register ( mpcore ) ICPIDR4
Register ICPIDR4 Details
Register ( mpcore ) ICPIDR5
Register ICPIDR5 Details
Register ( mpcore ) ICPIDR6
Register ICPIDR6 Details
Register ( mpcore ) ICPIDR7
Register ICPIDR7 Details
Register ( mpcore ) ICPIDR0
Register ICPIDR0 Details
Register ( mpcore ) ICPIDR1
Register ICPIDR1 Details
Register ( mpcore ) ICPIDR2
Register ICPIDR2 Details
Register ( mpcore ) ICPIDR3
Register ICPIDR3 Details
Register ( mpcore ) ICCIDR0
Register ICCIDR0 Details
Register ( mpcore ) ICCIDR1
Register ICCIDR1 Details
Register ( mpcore ) ICCIDR2
Register ICCIDR2 Details
Register ( mpcore ) ICCIDR3
Register ICCIDR3 Details
On-Chip Memory (ocm)
Register Summary
Register ( ocm ) OCM_PARITY_CTRL
Register OCM_PARITY_CTRL Details
Register ( ocm ) OCM_PARITY_ERRADDRESS
Register OCM_PARITY_ERRADDRESS Details
Register ( ocm ) OCM_IRQ_STS
Register OCM_IRQ_STS Details
Register ( ocm ) OCM_CONTROL
Register OCM_CONTROL Details
Quad-SPI Flash Controller (qspi)
Register Summary
Register ( qspi ) XQSPIPS_CR_OFFSET
Register XQSPIPS_CR_OFFSET Details
Register ( qspi ) XQSPIPS_SR_OFFSET
Register XQSPIPS_SR_OFFSET Details
Register ( qspi ) XQSPIPS_IER_OFFSET
Register XQSPIPS_IER_OFFSET Details
Register ( qspi ) XQSPIPS_IDR_OFFSET
Register XQSPIPS_IDR_OFFSET Details
Register ( qspi ) XQSPIPS_IMR_OFFSET
Register XQSPIPS_IMR_OFFSET Details
Register ( qspi ) XQSPIPS_ER_OFFSET
Register XQSPIPS_ER_OFFSET Details
Register ( qspi ) XQSPIPS_DR_OFFSET
Register XQSPIPS_DR_OFFSET Details
Register ( qspi ) XQSPIPS_TXD_00_OFFSET
Register XQSPIPS_TXD_00_OFFSET Details
Register ( qspi ) XQSPIPS_RXD_OFFSET
Register XQSPIPS_RXD_OFFSET Details
Register ( qspi ) XQSPIPS_SICR_OFFSET
Register XQSPIPS_SICR_OFFSET Details
Register ( qspi ) XQSPIPS_TXWR_OFFSET
Register XQSPIPS_TXWR_OFFSET Details
Register ( qspi ) RX_thres_REG
Register RX_thres_REG Details
Register ( qspi ) GPIO
Register GPIO Details
Register ( qspi ) LPBK_DLY_ADJ
Register LPBK_DLY_ADJ Details
Register ( qspi ) XQSPIPS_TXD_01_OFFSET
Register XQSPIPS_TXD_01_OFFSET Details
Register ( qspi ) XQSPIPS_TXD_10_OFFSET
Register XQSPIPS_TXD_10_OFFSET Details
Register ( qspi ) XQSPIPS_TXD_11_OFFSET
Register XQSPIPS_TXD_11_OFFSET Details
Register ( qspi ) XQSPIPS_LQSPI_CR_OFFSET
Register XQSPIPS_LQSPI_CR_OFFSET Details
Register ( qspi ) XQSPIPS_LQSPI_SR_OFFSET
Register XQSPIPS_LQSPI_SR_OFFSET Details
Register ( qspi ) MOD_ID
Register MOD_ID Details
SD Controller (sdio)
Register Summary
Register ( sdio ) SDMA_system_address_register
Register SDMA_system_address_register Details
Register ( sdio ) Block_Size_Block_Count
Register Block_Size_Block_Count Details
Register ( sdio ) Argument
Register Argument Details
Register ( sdio ) Transfer_Mode_Command
Register Transfer_Mode_Command Details
Register ( sdio ) Response0
Register Response0 to Response3 Details
Register ( sdio ) Buffer_Data_Port
Register Buffer_Data_Port Details
Register ( sdio ) Present_State
Register Present_State Details
Register ( sdio ) Host_control_Power_control_Block_Gap_Control_Wakeup_control
Register Host_control_Power_control_Block_Gap_Control_Wakeup_control Details
Register ( sdio ) Clock_Control_Timeout_control_Software_reset
Register Clock_Control_Timeout_control_Software_reset Details
Register ( sdio ) Normal_interrupt_status_Error_interrupt_status
Register Normal_interrupt_status_Error_interrupt_status Details
Register ( sdio ) Normal_interrupt_status_enable_Error_interrupt_status_enable
Register Normal_interrupt_status_enable_Error_interrupt_status_enable Details
Register ( sdio ) Normal_interrupt_signal_enable_Error_interrupt_signal_enable
Register Normal_interrupt_signal_enable_Error_interrupt_signal_enable Details
Register ( sdio ) Auto_CMD12_error_status
Register Auto_CMD12_error_status Details
Register ( sdio ) Capabilities
Register Capabilities Details
Register ( sdio ) Maximum_current_capabilities
Register Maximum_current_capabilities Details
Register ( sdio ) Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status
Register Force_event_for_AutoCmd12_Error_Status_Force_event_register_for_error_interrupt_status Details
Register ( sdio ) ADMA_error_status
Register ADMA_error_status Details
Register ( sdio ) ADMA_system_address
Register ADMA_system_address Details
Register ( sdio ) Boot_Timeout_control
Register Boot_Timeout_control Details
Register ( sdio ) Debug_Selection
Register Debug_Selection Details
Register ( sdio ) SPI_interrupt_support
Register SPI_interrupt_support Details
Register ( sdio ) Slot_interrupt_status_Host_controller_version
Register Slot_interrupt_status_Host_controller_version Details
System Level Control Registers (slcr)
Register Summary
Register ( slcr ) SCL
Register SCL Details
Register ( slcr ) SLCR_LOCK
Register SLCR_LOCK Details
Register ( slcr ) SLCR_UNLOCK
Register SLCR_UNLOCK Details
Register ( slcr ) SLCR_LOCKSTA
Register SLCR_LOCKSTA Details
Register ( slcr ) ARM_PLL_CTRL
Register ARM_PLL_CTRL Details
Register ( slcr ) DDR_PLL_CTRL
Register DDR_PLL_CTRL Details
Register ( slcr ) IO_PLL_CTRL
Register IO_PLL_CTRL Details
Register ( slcr ) PLL_STATUS
Register PLL_STATUS Details
Register ( slcr ) ARM_PLL_CFG
Register ARM_PLL_CFG Details
Register ( slcr ) DDR_PLL_CFG
Register DDR_PLL_CFG Details
Register ( slcr ) IO_PLL_CFG
Register IO_PLL_CFG Details
Register ( slcr ) ARM_CLK_CTRL
Register ARM_CLK_CTRL Details
Register ( slcr ) DDR_CLK_CTRL
Register DDR_CLK_CTRL Details
Register ( slcr ) DCI_CLK_CTRL
Register DCI_CLK_CTRL Details
Register ( slcr ) APER_CLK_CTRL
Register APER_CLK_CTRL Details
Register ( slcr ) USB0_CLK_CTRL
Register USB0_CLK_CTRL Details
Register ( slcr ) USB1_CLK_CTRL
Register USB1_CLK_CTRL Details
Register ( slcr ) GEM0_RCLK_CTRL
Register GEM0_RCLK_CTRL Details
Register ( slcr ) GEM1_RCLK_CTRL
Register GEM1_RCLK_CTRL Details
Register ( slcr ) GEM0_CLK_CTRL
Register GEM0_CLK_CTRL Details
Register ( slcr ) GEM1_CLK_CTRL
Register GEM1_CLK_CTRL Details
Register ( slcr ) SMC_CLK_CTRL
Register SMC_CLK_CTRL Details
Register ( slcr ) LQSPI_CLK_CTRL
Register LQSPI_CLK_CTRL Details
Register ( slcr ) SDIO_CLK_CTRL
Register SDIO_CLK_CTRL Details
Register ( slcr ) UART_CLK_CTRL
Register UART_CLK_CTRL Details
Register ( slcr ) SPI_CLK_CTRL
Register SPI_CLK_CTRL Details
Register ( slcr ) CAN_CLK_CTRL
Register CAN_CLK_CTRL Details
Register ( slcr ) CAN_MIOCLK_CTRL
Register CAN_MIOCLK_CTRL Details
Register ( slcr ) DBG_CLK_CTRL
Register DBG_CLK_CTRL Details
Register ( slcr ) PCAP_CLK_CTRL
Register PCAP_CLK_CTRL Details
Register ( slcr ) TOPSW_CLK_CTRL
Register TOPSW_CLK_CTRL Details
Register ( slcr ) FPGA0_CLK_CTRL
Register FPGA0_CLK_CTRL Details
Register ( slcr ) FPGA0_THR_CTRL
Register FPGA0_THR_CTRL Details
Register ( slcr ) FPGA0_THR_CNT
Register FPGA0_THR_CNT Details
Register ( slcr ) FPGA0_THR_STA
Register FPGA0_THR_STA Details
Register ( slcr ) FPGA1_CLK_CTRL
Register FPGA1_CLK_CTRL Details
Register ( slcr ) FPGA1_THR_CTRL
Register FPGA1_THR_CTRL Details
Register ( slcr ) FPGA1_THR_CNT
Register FPGA1_THR_CNT Details
Register ( slcr ) FPGA1_THR_STA
Register FPGA1_THR_STA Details
Register ( slcr ) FPGA2_CLK_CTRL
Register FPGA2_CLK_CTRL Details
Register ( slcr ) FPGA2_THR_CTRL
Register FPGA2_THR_CTRL Details
Register ( slcr ) FPGA2_THR_CNT
Register FPGA2_THR_CNT Details
Register ( slcr ) FPGA2_THR_STA
Register FPGA2_THR_STA Details
Register ( slcr ) FPGA3_CLK_CTRL
Register FPGA3_CLK_CTRL Details
Register ( slcr ) FPGA3_THR_CTRL
Register FPGA3_THR_CTRL Details
Register ( slcr ) FPGA3_THR_CNT
Register FPGA3_THR_CNT Details
Register ( slcr ) FPGA3_THR_STA
Register FPGA3_THR_STA Details
Register ( slcr ) CLK_621_TRUE
Register CLK_621_TRUE Details
Register ( slcr ) PSS_RST_CTRL
Register PSS_RST_CTRL Details
Register ( slcr ) DDR_RST_CTRL
Register DDR_RST_CTRL Details
Register ( slcr ) TOPSW_RST_CTRL
Register TOPSW_RST_CTRL Details
Register ( slcr ) DMAC_RST_CTRL
Register DMAC_RST_CTRL Details
Register ( slcr ) USB_RST_CTRL
Register USB_RST_CTRL Details
Register ( slcr ) GEM_RST_CTRL
Register GEM_RST_CTRL Details
Register ( slcr ) SDIO_RST_CTRL
Register SDIO_RST_CTRL Details
Register ( slcr ) SPI_RST_CTRL
Register SPI_RST_CTRL Details
Register ( slcr ) CAN_RST_CTRL
Register CAN_RST_CTRL Details
Register ( slcr ) I2C_RST_CTRL
Register I2C_RST_CTRL Details
Register ( slcr ) UART_RST_CTRL
Register UART_RST_CTRL Details
Register ( slcr ) GPIO_RST_CTRL
Register GPIO_RST_CTRL Details
Register ( slcr ) LQSPI_RST_CTRL
Register LQSPI_RST_CTRL Details
Register ( slcr ) SMC_RST_CTRL
Register SMC_RST_CTRL Details
Register ( slcr ) OCM_RST_CTRL
Register OCM_RST_CTRL Details
Register ( slcr ) FPGA_RST_CTRL
Register FPGA_RST_CTRL Details
Register ( slcr ) A9_CPU_RST_CTRL
Register A9_CPU_RST_CTRL Details
Register ( slcr ) RS_AWDT_CTRL
Register RS_AWDT_CTRL Details
Register ( slcr ) REBOOT_STATUS
Register REBOOT_STATUS Details
Register ( slcr ) BOOT_MODE
Register BOOT_MODE Details
Register ( slcr ) APU_CTRL
Register APU_CTRL Details
Register ( slcr ) WDT_CLK_SEL
Register WDT_CLK_SEL Details
Register ( slcr ) TZ_DMA_NS
Register TZ_DMA_NS Details
Register ( slcr ) TZ_DMA_IRQ_NS
Register TZ_DMA_IRQ_NS Details
Register ( slcr ) TZ_DMA_PERIPH_NS
Register TZ_DMA_PERIPH_NS Details
Register ( slcr ) PSS_IDCODE
Register PSS_IDCODE Details
Register ( slcr ) DDR_URGENT
Register DDR_URGENT Details
Register ( slcr ) DDR_CAL_START
Register DDR_CAL_START Details
Register ( slcr ) DDR_REF_START
Register DDR_REF_START Details
Register ( slcr ) DDR_CMD_STA
Register DDR_CMD_STA Details
Register ( slcr ) DDR_URGENT_SEL
Register DDR_URGENT_SEL Details
Register ( slcr ) DDR_DFI_STATUS
Register DDR_DFI_STATUS Details
Register ( slcr ) MIO_PIN_00
Register MIO_PIN_00 Details
Register ( slcr ) MIO_PIN_01
Register MIO_PIN_01 Details
Register ( slcr ) MIO_PIN_02
Register MIO_PIN_02 Details
Register ( slcr ) MIO_PIN_03
Register MIO_PIN_03 Details
Register ( slcr ) MIO_PIN_04
Register MIO_PIN_04 Details
Register ( slcr ) MIO_PIN_05
Register MIO_PIN_05 Details
Register ( slcr ) MIO_PIN_06
Register MIO_PIN_06 Details
Register ( slcr ) MIO_PIN_07
Register MIO_PIN_07 Details
Register ( slcr ) MIO_PIN_08
Register MIO_PIN_08 Details
Register ( slcr ) MIO_PIN_09
Register MIO_PIN_09 Details
Register ( slcr ) MIO_PIN_10
Register MIO_PIN_10 Details
Register ( slcr ) MIO_PIN_11
Register MIO_PIN_11 Details
Register ( slcr ) MIO_PIN_12
Register MIO_PIN_12 Details
Register ( slcr ) MIO_PIN_13
Register MIO_PIN_13 Details
Register ( slcr ) MIO_PIN_14
Register MIO_PIN_14 Details
Register ( slcr ) MIO_PIN_15
Register MIO_PIN_15 Details
Register ( slcr ) MIO_PIN_16
Register MIO_PIN_16 Details
Register ( slcr ) MIO_PIN_17
Register MIO_PIN_17 Details
Register ( slcr ) MIO_PIN_18
Register MIO_PIN_18 Details
Register ( slcr ) MIO_PIN_19
Register MIO_PIN_19 Details
Register ( slcr ) MIO_PIN_20
Register MIO_PIN_20 Details
Register ( slcr ) MIO_PIN_21
Register MIO_PIN_21 Details
Register ( slcr ) MIO_PIN_22
Register MIO_PIN_22 Details
Register ( slcr ) MIO_PIN_23
Register MIO_PIN_23 Details
Register ( slcr ) MIO_PIN_24
Register MIO_PIN_24 Details
Register ( slcr ) MIO_PIN_25
Register MIO_PIN_25 Details
Register ( slcr ) MIO_PIN_26
Register MIO_PIN_26 Details
Register ( slcr ) MIO_PIN_27
Register MIO_PIN_27 Details
Register ( slcr ) MIO_PIN_28
Register MIO_PIN_28 Details
Register ( slcr ) MIO_PIN_29
Register MIO_PIN_29 Details
Register ( slcr ) MIO_PIN_30
Register MIO_PIN_30 Details
Register ( slcr ) MIO_PIN_31
Register MIO_PIN_31 Details
Register ( slcr ) MIO_PIN_32
Register MIO_PIN_32 Details
Register ( slcr ) MIO_PIN_33
Register MIO_PIN_33 Details
Register ( slcr ) MIO_PIN_34
Register MIO_PIN_34 Details
Register ( slcr ) MIO_PIN_35
Register MIO_PIN_35 Details
Register ( slcr ) MIO_PIN_36
Register MIO_PIN_36 Details
Register ( slcr ) MIO_PIN_37
Register MIO_PIN_37 Details
Register ( slcr ) MIO_PIN_38
Register MIO_PIN_38 Details
Register ( slcr ) MIO_PIN_39
Register MIO_PIN_39 Details
Register ( slcr ) MIO_PIN_40
Register MIO_PIN_40 Details
Register ( slcr ) MIO_PIN_41
Register MIO_PIN_41 Details
Register ( slcr ) MIO_PIN_42
Register MIO_PIN_42 Details
Register ( slcr ) MIO_PIN_43
Register MIO_PIN_43 Details
Register ( slcr ) MIO_PIN_44
Register MIO_PIN_44 Details
Register ( slcr ) MIO_PIN_45
Register MIO_PIN_45 Details
Register ( slcr ) MIO_PIN_46
Register MIO_PIN_46 Details
Register ( slcr ) MIO_PIN_47
Register MIO_PIN_47 Details
Register ( slcr ) MIO_PIN_48
Register MIO_PIN_48 Details
Register ( slcr ) MIO_PIN_49
Register MIO_PIN_49 Details
Register ( slcr ) MIO_PIN_50
Register MIO_PIN_50 Details
Register ( slcr ) MIO_PIN_51
Register MIO_PIN_51 Details
Register ( slcr ) MIO_PIN_52
Register MIO_PIN_52 Details
Register ( slcr ) MIO_PIN_53
Register MIO_PIN_53 Details
Register ( slcr ) MIO_LOOPBACK
Register MIO_LOOPBACK Details
Register ( slcr ) MIO_MST_TRI0
Register MIO_MST_TRI0 Details
Register ( slcr ) MIO_MST_TRI1
Register MIO_MST_TRI1 Details
Register ( slcr ) SD0_WP_CD_SEL
Register SD0_WP_CD_SEL Details
Register ( slcr ) SD1_WP_CD_SEL
Register SD1_WP_CD_SEL Details
Register ( slcr ) LVL_SHFTR_EN
Register LVL_SHFTR_EN Details
Register ( slcr ) OCM_CFG
Register OCM_CFG Details
Register ( slcr ) Reserved
Register Reserved Details
Register ( slcr ) GPIOB_CTRL
Register GPIOB_CTRL Details
Register ( slcr ) GPIOB_CFG_CMOS18
Register GPIOB_CFG_CMOS18 Details
Register ( slcr ) GPIOB_CFG_CMOS25
Register GPIOB_CFG_CMOS25 Details
Register ( slcr ) GPIOB_CFG_CMOS33
Register GPIOB_CFG_CMOS33 Details
Register ( slcr ) GPIOB_CFG_HSTL
Register GPIOB_CFG_HSTL Details
Register ( slcr ) GPIOB_DRVR_BIAS_CTRL
Register GPIOB_DRVR_BIAS_CTRL Details
Register ( slcr ) DDRIOB_ADDR0
Register DDRIOB_ADDR0 Details
Register ( slcr ) DDRIOB_ADDR1
Register DDRIOB_ADDR1 Details
Register ( slcr ) DDRIOB_DATA0
Register DDRIOB_DATA0 Details
Register ( slcr ) DDRIOB_DATA1
Register DDRIOB_DATA1 Details
Register ( slcr ) DDRIOB_DIFF0
Register DDRIOB_DIFF0 Details
Register ( slcr ) DDRIOB_DIFF1
Register DDRIOB_DIFF1 Details
Register ( slcr ) DDRIOB_CLOCK
Register DDRIOB_CLOCK Details
Register ( slcr ) DDRIOB_DRIVE_SLEW_ADDR
Register DDRIOB_DRIVE_SLEW_ADDR Details
Register ( slcr ) DDRIOB_DRIVE_SLEW_DATA
Register DDRIOB_DRIVE_SLEW_DATA Details
Register ( slcr ) DDRIOB_DRIVE_SLEW_DIFF
Register DDRIOB_DRIVE_SLEW_DIFF Details
Register ( slcr ) DDRIOB_DRIVE_SLEW_CLOCK
Register DDRIOB_DRIVE_SLEW_CLOCK Details
Register ( slcr ) DDRIOB_DDR_CTRL
Register DDRIOB_DDR_CTRL Details
Register ( slcr ) DDRIOB_DCI_CTRL
Register DDRIOB_DCI_CTRL Details
Register ( slcr ) DDRIOB_DCI_STATUS
Register DDRIOB_DCI_STATUS Details
Static Memory Controller (pl353)
Register Summary
Register ( pl353 ) XNANDPS_MEMC_STATUS_OFFSET
Register XNANDPS_MEMC_STATUS_OFFSET Details
Register ( pl353 ) XNANDPS_MEMC_IF_CONFIG_OFFSET
Register XNANDPS_MEMC_IF_CONFIG_OFFSET Details
Register ( pl353 ) XNANDPS_MEMC_SET_CONFIG_OFFSET
Register XNANDPS_MEMC_SET_CONFIG_OFFSET Details
Register ( pl353 ) XNANDPS_MEMC_CLR_CONFIG_OFFSET
Register XNANDPS_MEMC_CLR_CONFIG_OFFSET Details
Register ( pl353 ) XNANDPS_DIRECT_CMD_OFFSET
Register XNANDPS_DIRECT_CMD_OFFSET Details
Register ( pl353 ) XNANDPS_SET_CYCLES_OFFSET
Register XNANDPS_SET_CYCLES_OFFSET Details
Register ( pl353 ) XNANDPS_SET_OPMODE_OFFSET
Register XNANDPS_SET_OPMODE_OFFSET Details
Register ( pl353 ) XNANDPS_REFRESH_PERIOD_0_OFFSET
Register XNANDPS_REFRESH_PERIOD_0_OFFSET Details
Register ( pl353 ) XNANDPS_REFRESH_PERIOD_1_OFFSET
Register XNANDPS_REFRESH_PERIOD_1_OFFSET Details
Register ( pl353 ) XNANDPS_IF0_CHIP_0_CONFIG_OFFSET
Register XNANDPS_IF0_CHIP_0_CONFIG_OFFSET Details
Register ( pl353 ) XNANDPS_OPMODE
Register XNANDPS_OPMODE Details
Register ( pl353 ) XNANDPS_IF0_CHIP_1_CONFIG_OFFSET
Register XNANDPS_IF0_CHIP_1_CONFIG_OFFSET Details
Register ( pl353 ) opmode0_1
Register opmode0_1 Details
Register ( pl353 ) XNANDPS_IF1_CHIP_0_CONFIG_OFFSET
Register XNANDPS_IF1_CHIP_0_CONFIG_OFFSET Details
Register ( pl353 ) opmode1_0
Register opmode1_0 Details
Register ( pl353 ) XNANDPS_USER_STATUS_OFFSET
Register XNANDPS_USER_STATUS_OFFSET Details
Register ( pl353 ) XNANDPS_USER_CONFIG_OFFSET
Register XNANDPS_USER_CONFIG_OFFSET Details
Register ( pl353 ) XNANDPS_IF1_ECC_OFFSET
Register XNANDPS_IF1_ECC_OFFSET Details
Register ( pl353 ) ecc_memcfg_1
Register ecc_memcfg_1 Details
Register ( pl353 ) ecc_memcommand1_1
Register ecc_memcommand1_1 Details
Register ( pl353 ) ecc_memcommand2_1
Register ecc_memcommand2_1 Details
Register ( pl353 ) ecc_addr0_1
Register ecc_addr0_1 Details
Register ( pl353 ) ecc_addr1_1
Register ecc_addr1_1 Details
Register ( pl353 ) ecc_value0_1
Register ecc_value0_1 Details
Register ( pl353 ) ecc_value1_1
Register ecc_value1_1 Details
Register ( pl353 ) ecc_value2_1
Register ecc_value2_1 Details
Register ( pl353 ) ecc_value3_1
Register ecc_value3_1 Details
SPI Controller (SPI)
Register Summary
Register ( SPI ) XSPIPS_CR_OFFSET
Register XSPIPS_CR_OFFSET Details
Register ( SPI ) XSPIPS_SR_OFFSET
Register XSPIPS_SR_OFFSET Details
Register ( SPI ) XSPIPS_IER_OFFSET
Register XSPIPS_IER_OFFSET Details
Register ( SPI ) XSPIPS_IDR_OFFSET
Register XSPIPS_IDR_OFFSET Details
Register ( SPI ) XSPIPS_IMR_OFFSET
Register XSPIPS_IMR_OFFSET Details
Register ( SPI ) XSPIPS_ER_OFFSET
Register XSPIPS_ER_OFFSET Details
Register ( SPI ) XSPIPS_DR_OFFSET
Register XSPIPS_DR_OFFSET Details
Register ( SPI ) XSPIPS_TXD_OFFSET
Register XSPIPS_TXD_OFFSET Details
Register ( SPI ) XSPIPS_RXD_OFFSET
Register XSPIPS_RXD_OFFSET Details
Register ( SPI ) XSPIPS_SICR_OFFSET
Register XSPIPS_SICR_OFFSET Details
Register ( SPI ) XSPIPS_TXWR_OFFSET
Register XSPIPS_TXWR_OFFSET Details
Register ( SPI ) RX_thres_reg0
Register RX_thres_reg0 Details
Register ( SPI ) Mod_id_reg0
Register Mod_id_reg0 Details
System Watchdog Timer (swdt)
Register Summary
Register ( swdt ) XWDTPS_ZMR_OFFSET
Register XWDTPS_ZMR_OFFSET Details
Register ( swdt ) XWDTPS_CCR_OFFSET
Register XWDTPS_CCR_OFFSET Details
Register ( swdt ) XWDTPS_RESTART_OFFSET
Register XWDTPS_RESTART_OFFSET Details
Register ( swdt ) XWDTPS_SR_OFFSET
Register XWDTPS_SR_OFFSET Details
Triple Timer Counter (ttc)
Register Summary
Register ( ttc ) XTTCPS_CLK_CNTRL_OFFSET
Register XTTCPS_CLK_CNTRL_OFFSET Details
Register ( ttc ) Clock_Control_2
Register Clock_Control_2 Details
Register ( ttc ) Clock_Control_3
Register Clock_Control_3 Details
Register ( ttc ) XTTCPS_CNT_CNTRL_OFFSET
Register XTTCPS_CNT_CNTRL_OFFSET Details
Register ( ttc ) Counter_Control_2
Register Counter_Control_2 Details
Register ( ttc ) Counter_Control_3
Register Counter_Control_3 Details
Register ( ttc ) XTTCPS_COUNT_VALUE_OFFSET
Register XTTCPS_COUNT_VALUE_OFFSET Details
Register ( ttc ) Counter_Value_2
Register Counter_Value_2 Details
Register ( ttc ) Counter_Value_3
Register Counter_Value_3 Details
Register ( ttc ) XTTCPS_INTERVAL_VAL_OFFSET
Register XTTCPS_INTERVAL_VAL_OFFSET Details
Register ( ttc ) Interval_Counter_2
Register Interval_Counter_2 Details
Register ( ttc ) Interval_Counter_3
Register Interval_Counter_3 Details
Register ( ttc ) XTTCPS_MATCH_0_OFFSET
Register XTTCPS_MATCH_0_OFFSET Details
Register ( ttc ) Match_1_Counter_2
Register Match_1_Counter_2 Details
Register ( ttc ) Match_1_Counter_3
Register Match_1_Counter_3 Details
Register ( ttc ) XTTCPS_MATCH_1_OFFSET
Register XTTCPS_MATCH_1_OFFSET Details
Register ( ttc ) Match_2_Counter_2
Register Match_2_Counter_2 Details
Register ( ttc ) Match_2_Counter_3
Register Match_2_Counter_3 Details
Register ( ttc ) XTTCPS_MATCH_2_OFFSET
Register XTTCPS_MATCH_2_OFFSET Details
Register ( ttc ) Match_3_Counter_2
Register Match_3_Counter_2 Details
Register ( ttc ) Match_3_Counter_3
Register Match_3_Counter_3 Details
Register ( ttc ) XTTCPS_ISR_OFFSET
Register XTTCPS_ISR_OFFSET Details
Register ( ttc ) Interrupt_Register_2
Register Interrupt_Register_2 Details
Register ( ttc ) Interrupt_Register_3
Register Interrupt_Register_3 Details
Register ( ttc ) XTTCPS_IER_OFFSET
Register XTTCPS_IER_OFFSET Details
Register ( ttc ) Interrupt_Enable_2
Register Interrupt_Enable_2 Details
Register ( ttc ) Interrupt_Enable_3
Register Interrupt_Enable_3 Details
Register ( ttc ) Event_Control_Timer_1
Register Event_Control_Timer_1 Details
Register ( ttc ) Event_Control_Timer_2
Register Event_Control_Timer_2 Details
Register ( ttc ) Event_Control_Timer_3
Register Event_Control_Timer_3 Details
Register ( ttc ) Event_Register_1
Register Event_Register_1 Details
Register ( ttc ) Event_Register_2
Register Event_Register_2 Details
Register ( ttc ) Event_Register_3
Register Event_Register_3 Details
UART Controller (UART)
Register Summary
Register ( UART ) XUARTPS_CR_OFFSET
Register XUARTPS_CR_OFFSET Details
Register ( UART ) XUARTPS_MR_OFFSET
Register XUARTPS_MR_OFFSET Details
Register ( UART ) XUARTPS_IER_OFFSET
Register XUARTPS_IER_OFFSET Details
Register ( UART ) XUARTPS_IDR_OFFSET
Register XUARTPS_IDR_OFFSET Details
Register ( UART ) XUARTPS_IMR_OFFSET
Register XUARTPS_IMR_OFFSET Details
Register ( UART ) XUARTPS_ISR_OFFSET
Register XUARTPS_ISR_OFFSET Details
Register ( UART ) XUARTPS_BAUDGEN_OFFSET
Register XUARTPS_BAUDGEN_OFFSET Details
Register ( UART ) XUARTPS_RXTOUT_OFFSET
Register XUARTPS_RXTOUT_OFFSET Details
Register ( UART ) XUARTPS_RXWM_OFFSET
Register XUARTPS_RXWM_OFFSET Details
Register ( UART ) XUARTPS_MODEMCR_OFFSET
Register XUARTPS_MODEMCR_OFFSET Details
Register ( UART ) XUARTPS_MODEMSR_OFFSET
Register XUARTPS_MODEMSR_OFFSET Details
Register ( UART ) XUARTPS_SR_OFFSET
Register XUARTPS_SR_OFFSET Details
Register ( UART ) XUARTPS_FIFO_OFFSET
Register XUARTPS_FIFO_OFFSET Details
Register ( UART ) Baud_rate_divider_reg0
Register Baud_rate_divider_reg0 Details
Register ( UART ) Flow_delay_reg0
Register Flow_delay_reg0 Details
Register ( UART ) Tx_FIFO_trigger_level0
Register Tx_FIFO_trigger_level0 Details
USB Controller (usb)
Register Summary
Register ( usb ) ID
Register ID Details
Register ( usb ) HWGENERAL
Register HWGENERAL Details
Register ( usb ) HWHOST
Register HWHOST Details
Register ( usb ) HWDEVICE
Register HWDEVICE Details
Register ( usb ) HWTXBUF
Register HWTXBUF Details
Register ( usb ) HWRXBUF
Register HWRXBUF Details
Register ( usb ) GPTIMER0LD
Register GPTIMER0LD Details
Register ( usb ) GPTIMER0CTRL
Register GPTIMER0CTRL Details
Register ( usb ) GPTIMER1LD
Register GPTIMER1LD Details
Register ( usb ) GPTIMER1CTRL
Register GPTIMER1CTRL Details
Register ( usb ) SBUSCFG
Register SBUSCFG Details
Register ( usb ) CAPLENGTH_HCIVERSION
Register CAPLENGTH_HCIVERSION Details
Register ( usb ) HCSPARAMS
Register HCSPARAMS Details
Register ( usb ) HCCPARAMS
Register HCCPARAMS Details
Register ( usb ) DCIVERSION
Register DCIVERSION Details
Register ( usb ) DCCPARAMS
Register DCCPARAMS Details
Register ( usb ) XUSBPS_CMD_OFFSET
Register XUSBPS_CMD_OFFSET Details
Register ( usb ) XUSBPS_ISR_OFFSET
Register XUSBPS_ISR_OFFSET Details
Register ( usb ) XUSBPS_IER_OFFSET
Register XUSBPS_IER_OFFSET Details
Register ( usb ) XUSBPS_FRAME_OFFSET
Register XUSBPS_FRAME_OFFSET Details
Register ( usb ) XUSBPS_LISTBASE_OFFSET
Register XUSBPS_LISTBASE_OFFSET Details
Register ( usb ) XUSBPS_ASYNCLISTADDR_OFFSET
Register XUSBPS_ASYNCLISTADDR_OFFSET Details
Register ( usb ) XUSBPS_TTCTRL_OFFSET
Register XUSBPS_TTCTRL_OFFSET Details
Register ( usb ) XUSBPS_BURSTSIZE_OFFSET
Register XUSBPS_BURSTSIZE_OFFSET Details
Register ( usb ) XUSBPS_TXFILL_OFFSET
Register XUSBPS_TXFILL_OFFSET Details
Register ( usb ) TXTTFILLTUNING
Register TXTTFILLTUNING Details
Register ( usb ) IC_USB
Register IC_USB Details
Register ( usb ) XUSBPS_ULPIVIEW_OFFSET
Register XUSBPS_ULPIVIEW_OFFSET Details
Register ( usb ) XUSBPS_EPNAKISR_OFFSET
Register XUSBPS_EPNAKISR_OFFSET Details
Register ( usb ) XUSBPS_EPNAKIER_OFFSET
Register XUSBPS_EPNAKIER_OFFSET Details
Register ( usb ) CONFIGFLAG
Register CONFIGFLAG Details
Register ( usb ) XUSBPS_PORTSCR1_OFFSET
Register XUSBPS_PORTSCR1_OFFSET Details
Register ( usb ) XUSBPS_OTGCSR_OFFSET
Register XUSBPS_OTGCSR_OFFSET Details
Register ( usb ) XUSBPS_MODE_OFFSET
Register XUSBPS_MODE_OFFSET Details
Register ( usb ) XUSBPS_EPSTAT_OFFSET
Register XUSBPS_EPSTAT_OFFSET Details
Register ( usb ) XUSBPS_EPPRIME_OFFSET
Register XUSBPS_EPPRIME_OFFSET Details
Register ( usb ) XUSBPS_EPFLUSH_OFFSET
Register XUSBPS_EPFLUSH_OFFSET Details
Register ( usb ) XUSBPS_EPRDY_OFFSET
Register XUSBPS_EPRDY_OFFSET Details
Register ( usb ) XUSBPS_EPCOMPL_OFFSET
Register XUSBPS_EPCOMPL_OFFSET Details
Register ( usb ) XUSBPS_EPCR0_OFFSET
Register XUSBPS_EPCR0_OFFSET Details
Register ( usb ) ENDPTCTRL1
Register ENDPTCTRL1 to ENDPTCTRL11 Details
Access Types Legend
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
Device User Guides
Zynq 7000 SoC Product Page
Xilinx Design Tools: Release Notes, Installation, and Licensing
AMD Forums and Wiki Links
AMD git Websites
Solution Centers
References
Zynq 7000 SoC Documents
PL Documents – Device and Boards
Additional Zynq 7000 SoC Documents
Software Programming Documents
git Information
Design Tool Resources
AMD Vivado Design Suite
AMD ISE Design Suite
AMD Embedded Development Kit (EDK)
ChipScope Pro Documentation
AMD Problem Solvers
Third-Party IP and Standards Documents
Please Read: Important Legal Notices
Additional Resources and Legal Notices
Finding Additional Documentation
Documentation Portal
Documentation Navigator
Design Hubs
Support Resources
Device User Guides
Zynq 7000 SoC Product Page
Xilinx Design Tools: Release Notes, Installation, and Licensing
AMD Forums and Wiki Links
AMD git Websites
Solution Centers
References
Zynq 7000 SoC Documents
PL Documents – Device and Boards
Additional Zynq 7000 SoC Documents
Software Programming Documents
git Information
Design Tool Resources
AMD Vivado Design Suite
AMD ISE Design Suite
AMD Embedded Development Kit (EDK)
ChipScope Pro Documentation
AMD Problem Solvers
Third-Party IP and Standards Documents
Please Read: Important Legal Notices

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