Special Considerations for XQ Ruggedized FPGAs - UG584

Using LVAUX Mode in XQ Ruggedized UltraScale+ Devices for Airborne Systems Design Guide (UG584)
Document ID
UG584
Release Date
2024-05-03
Revision
1.1 English

XQ Ruggedized Virtex UltraScale+ FPGAs Package Pin and Supply Names

The XQ ruggedized Virtex UltraScale+ devices do not have HD I/O, and their packages use the common VCCAUX_IO pin name, rather than the special VCCAUX_HPIO pin name. Thus, these XQ ruggedized Virtex UltraScale+ device VCCAUX_IO pins are inherently isolated to supply auxiliary power to only the HP I/O. References and LVAUX mode recommendations for the VCCAUX_HPIO supply/pins through the remainder of this document are applicable to the XQ ruggedized Virtex UltraScale+ device VCCAUX_IO supply/pins. The VCCAUX_HDIO supply/pins references and recommendations in this document do not apply to XQ ruggedized Virtex UltraScale+ devices.

The following table summarizes HP I/O and HD I/O pin names, supply names, and recommendations for the XQ ruggedized UltraScale+ devices.

Table 1. Package Pin and Supply Names for Normal and LVAUX Mode by Family
Device Family I/O Type XQ Ruggedized Package Pin Names Auxiliary HP I/O and HD I/O Banks Supply Names and Voltages
I/O Pins Normal Mode Supply

 LVAUX Mode Supplies
Pin Name Supply Name Supply Voltage Supply Name Supply Voltage
XQ Ruggedized Zynq UltraScale+ Devices HP I/O VCCAUX_HPIO 1 VCCAUX_IO 1 1.8V 1 VCCAUX_HPIO 2 1.2V 2
HD I/O VCCAUX_HDIO 1 VCCAUX_HDIO 2 1.8V 2
XQ Ruggedized Kintex UltraScale+ Devices HP I/O VCCAUX_HPIO 1 VCCAUX_IO 1 1.8V 1 VCCAUX_HPIO 2 1.2V 2
HD I/O VCCAUX_HDIO 1 VCCAUX_HDIO 2 1.8V 2
XQ Ruggedized Virtex UltraScale+ Devices HP I/O VCCAUX_IO 3 VCCAUX_IO 3 1.8V 3 VCCAUX_HPIO 4

(for VCCAUX_IO pins)

 1.2V 4
HD I/O 5 N/A N/A N/A N/A N/A
  1. In normal mode, XQ Ruggedized Zynq UltraScale+ and XQ Ruggedized Kintex UltraScale+ device VCCAUX_HPIO, VCCAUX_HDIO, and VCCAUX pins must be tied together; and VCCAUX_IO and VCCAUX must be supplied from one 1.8V power supply.
  2. In LVAUX mode, XQ Ruggedized Zynq UltraScale+ and XQ Ruggedized Kintex UltraScale+ device VCCAUX_HDIO and VCCAUX pins must be tied together; and VCCAUX_IO and VCCAUX must be supplied from one 1.8V power supply. A separate 1.2V VCCAUX_HPIO source must supply the VCCAUX_HPIO pins.
  3. In normal mode, XQ Ruggedized Virtex UltraScale+ device VCCAUX_IO and VCCAUX pins must be tied together; and VCCAUX_IO and VCCAUX must be supplied from one 1.8V power supply.
  4. In LVAUX mode, XQ Ruggedized Virtex UltraScale+ device VCCAUX pins must be supplied from a 1.8V VCCAUX power supply, and a separate 1.2V VCCAUX_HPIO source must supply the VCCAUX_IO pins.
  5. XQ Ruggedized Virtex UltraScale+ devices do not have HD I/O.

Managing the Bank 0 VCCO_0 in XQ Ruggedized UltraScale+ FPGAs

In XQ ruggedized Kintex UltraScale+ and Virtex UltraScale+ FPGAs, bank 0 is reserved for specific power on and configuration signals. VCCO_0 is the supply voltage for bank 0. For VCCO_0, the minimum recommended operating voltage for power-up through configuration is 1.425V. During configuration, VCCO_0 must be set to 1.5V or 1.8V.

XQ Ruggedized UltraScale+ FPGA Configuration Modes

For XQ ruggedized Kintex UltraScale+ and Virtex UltraScale+ FPGAs, the configuration interfaces that use bank 65 are not supported in LVAUX mode. This is because bank 65 requires a greater voltage than the LVAUX mode supports. The following FPGA configuration modes are not supported in LVAUX mode:

  • Master SPI (x8 (dual x4))
  • Master BPI (x8, x16)
  • Slave SelectMAP (x8, x16, x32)

The following configuration modes are supported for LVAUX mode:

  • Slave serial without DOUT
  • JTAG
  • Master SPI (x1) without EMCCLK and DOUT
  • Master SPI (x2, x4) without EMCCLK