The low-rate residual SEL was characterized though extensive neutron and proton beam testing on AMD Zynq™ UltraScale+™ devices, AMD Kintex™ UltraScale+™ FPGAs, and AMD Virtex™ UltraScale+™ FPGAs.
The impacted circuits in the device reside in the System Monitor (SYSMON) block and the high-performance (HP) I/O auxiliary block that controls level shifting and digitally-controlled impedance for the HP I/O pins. When following standard PCB guidelines and data sheet specifications for XC devices, these blocks are powered by the VCCAUX, VCC_PSAUX, and the VCCAUX_IO supplies that are connected together and powered at 1.8V. The number of SYSMON blocks depends on the device. See the Defense-Grade UltraScale Architecture Data Sheet: Overview (DS895) for how many SYSMON blocks are available by device. All UltraScale+ devices have an HP I/O auxiliary block for each HP I/O pin.
An SEL event manifests in an increased current draw on the supply line of interest. The only way to clear that increased SEL current is to power cycle the affected voltage line to a point below the holding voltage of 1V. Applying this approach on an XC device, where all the affected power rails are connected to 1.8V, would trigger power-on reset. Employing a more granular power system that independently controls the processing system (PS) and programmable logic (PL) affected supplies can allow for independent PS and PL recovery from an SEL event.