SEL Mitigation Options Overview - UG584

Using LVAUX Mode in XQ Ruggedized UltraScale+ Devices for Airborne Systems Design Guide (UG584)
Document ID
UG584
Release Date
2024-05-03
Revision
1.1 English

Based on assessment of the SEL rate for the system, and considering the impact of an SEL on the system, a system architect can assess whether an SEL mitigation approach is required. Use the following information to select an appropriate mitigation approach, which could include using the device in LVAUX mode. Mitigation approaches should consider the following guidance:

  • Monitor the junction temperature of the device.
    • Monitor for temperatures outside the range of the recommended operating minimum and maximum junction temperatures for the device (Tj) available in the Recommended Operating Conditions tables in the UltraScale+ device data sheets.
    • Monitor the SYSMON temperature readings in the PS and PL when designing with either the Zynq UltraScale+ MPSoCs or Zynq UltraScale+ RFSoCs.
  • Monitor for flat-line (stuck-at) SYSMON readings.
    • Junction temperature
    • Other ADC readings
  • Monitor current on the three rails and look for current step on 1.8V auxiliary supplies.
    • Monitor the current on the combined sum of 1.8V auxiliary supply rail currents.
      • VCCAUX
      • VCCAUX_IO
      • VCC_PSAUX
    • Additional separate monitoring for each independent auxiliary supply rail. For self-monitoring, use the PL SYSMON ADC for measuring 1.8V auxiliary current(s).
      • Use dedicated VP/VN pins to monitor the total 1.8V auxiliary current.
      • Other analog inputs can be used for additional monitoring.
    • Following device initialization, monitor for SEL current step that is greater than 100 mA within less than 10 μs.
      • Monitor step should be functionally tested over environmental conditions.
      • The monitor step value could need adjustment to ensure no false SEL triggers occur as a result of dynamic behavior in the specific design implementation.
  • Run monitor code in platform management unit (PMU) for Zynq UltraScale+ devices, or triple-modular redundancy (TMR) MicroBlaze™ processor in UltraScale+ FPGAs.
    • Use a pulsing output signal to indicate status of good.
    • Use a steady High or Low output signal to indicate SEL or another anomalous condition.
  • Power cycle to clear the increased SEL current draw.
    • The affected power supply rail must fall below 1V to clear the SEL condition.
    • Power cycling on the affected PL supplies will trigger a power-on reset.
    • If necessary, the PS and PL can be cycled independently (requires additional guidance).
  • Monitor and log events at the system level and store in non-volatile memory.
    • Long-term reliability could be impacted as a result of SEL in the HP I/O auxiliary block.
    • SEL events in SYSMON have no impact on device reliability.
    • Logging of SEL events to non-volatile memory can be a valuable maintenance tool.
  • Develop SEL mitigation circuits that monitor temperature changes and reduces voltage to a level that clears an SEL as described in patent US9793899B1.

SEL rates can be managed independently in the SoC. Partitioning the device-level SEL into a PS SEL rate and a PL SEL rate allows for the possibility of independent power cycling of the PS and PL. This approach requires additional guidance beyond the scope of this document. It also adds complexity to the power-on and booting of the device including an additional impact to any PS APU and RPU embedded code and the PL design.