Power Guidelines - Power Guidelines

The following table describes the typical quiescent supply current from the V_{CCAUX_HPIO} and V_{CCAUX_HDIO} power supplies. These numbers are pessimistic estimates. The actual quiescent supply current will most likely be lower than the values shown here.

Table 1. Typical Quiescent Supply Current
Symbol	Description^{1, 2, 3}	Device	Speed Grade and V_CCINT Operating Voltages				Units
			0.85V		0.72V
			-2	-1	-2	-1
XQ Ruggedized Kintex UltraScale+ FPGAs
I_{CCAUX_HPIOQ} and I_{CCAUX_HDIOQ}	Quiescent V_{CCAUX_HPIO} and V_{CCAUX_HDIO} supply current	XQKU5P	32	32	N/A	32	mA
I_{CCAUX_HPIOQ} and I_{CCAUX_HDIOQ}	Quiescent V_{CCAUX_HPIO} and V_{CCAUX_HDIO} supply current	XQKU15P	74	74	N/A	74	mA
XQ Ruggedized Virtex UltraScale+ FPGAs
I_{CCAUX_HPIOQ}	Quiescent V_{CCAUX_HPIO}	XQVU3P	62	62	62	62	mA
		XQVU7P	124	124	124	124	mA
		XQVU11P	79	79	79	79	mA
XQ Ruggedized Zynq UltraScale+ MPSoCs
I_{CCAUX_HPIOQ} and I_{CCAUX_HDIOQ}	V_{CCAUX_HPIO} and V_{CCAUX_HDIO} supply current	XQZU3EG	26	26	N/A	26	mA
		XQZU5EV	32	32	N/A	32	mA
		XQZU7EV	56	56	N/A	56	mA
		XQZU9EG	33	33	N/A	33	mA
		XQZU11EG	56	56	N/A	56	mA
		XQZU15EG	33	33	N/A	33	mA
		XQZU19EG	74	74	N/A	74	mA
XQ Ruggedized Zynq UltraScale+ RFSoCs
I_{CCAUX_HPIOQ} and I_{CCAUX_HDIOQ}	V_{CCAUX_HPIO} and V_{CCAUX_HDIO} supply current	XQZU21DR	58	58	N/A	58	mA
		XQZU28DR	58	58	N/A	58	mA
		XQZU29DR	58	58	N/A	58	mA
		XQZU48DR	58	58	58	58	mA
		XQZU49DR	58	58	58	58	mA
		XQZU65DR	36	36	36	36	mA
		XQZU67DR	36	36	36	36	mA
Typical values are specified at nominal voltage, 85°C junction temperatures (T_j) with single-ended SelectIO™ resources. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, and all I/O pins are 3-state and floating. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to estimate static power consumption for conditions or supplies other than those specified. See Estimating Power to estimate power consumption of HP I/O banks and HD I/O banks in LVAUX mode. Typical values depend upon your configuration. To accurately estimate all PS and PL supply currents, use XPE.

PL/FPGA Power-On/Off Power Supply Sequencing

To achieve minimum current draw and to ensure that the I/Os are 3-stated at power-on, use the following recommended power-on sequence:

V_CCINT
V_{CCINT_IO} and V_CCBRAM
V_CCAUX and V_{CCAUX_HDIO}
V_{CCAUX_HPIO}
V_CCO

The recommended power-off sequence is the reverse of the power-on sequence. If V_CCINT and V_{CCINT_IO}/V_CCBRAM have the same recommended voltage levels, they can be powered by the same supply and ramped simultaneously. V_{CCINT_IO} must be connected to V_CCBRAM. V_CCAUX/V_{CCAUX_HDIO} and V_CCO for HD I/O banks have the same recommended voltage levels and can be powered by the same supply and ramped simultaneously. V_{CCAUX_HPIO} and V_CCO for HP I/O banks have the same recommended voltage levels, and they must be powered by the same supply and ramped simultaneously. V_CCAUX must be connected to V_{CCAUX_HDIO}. V_CCADC and V_REF can be powered at any time and have no power-up sequencing requirements.

Power Supply Requirements

The following table shows the minimum current, in addition to I_CCQ maximum, required by each UltraScale+ device for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on and reset threshold voltages. These numbers are pessimistic estimates. The actual power-on current will most likely be lower than the values shown here. The device must not be configured until after V_CCINT is applied. After the device is initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) and instructions from Estimating Power to estimate current drain on these supplies. XPE can be used to estimate power-on current for all voltage supplies.

Table 2. Power-on Current by Device
I_CC Min =	I_CCINTMIN	I_{CCINT_IOMIN} + I_CCBRAMMIN	I_CCOMIN	I_CCAUXMIN	I_{CCAUX_HDIOMIN}	I_{CCAUX_HPIOMIN}	I_CCSDFECMIN	Units
I_CCQ +	I_CCINTQ +	I_CCBRAMQ + I_{CCINT_IOQ} +	I_CCOQ +	I_CCAUXQ +	I_{CCAUX_IOQ} +	I_{CCAUX_IOQ} +	I_CCSDFECQ +	Units
XQ Ruggedized Kintex UltraScale+ FPGAs
XQKU5P	770	305	50	515	515	515	N/A	mA
XQKU15P	3433	1145	96	1240	1240	1240	N/A	mA
XQ Ruggedized Virtex UltraScale+ FPGAs
XQVU3P	2000	670	50	350	350	350	N/A	mA
XQVU7P	4000	1340	100	700	700	700	N/A	mA
XQVU11P	6549	2194	164	1146	1146	1146	N/A	mA
XQ Ruggedized Zynq UltraScale+ MPSoCs
XQZU3EG	464	155	50	111	111	111	N/A	mA
XQZU5EV	770	257	50	386	386	386	N/A	mA
XQZU7EV	1514	505	50	362	362	362	N/A	mA
XQZU9EG	1800	600	50	650	650	650	N/A	mA
XQZU11EG	1961	654	55	709	709	709	N/A	mA
XQZU15EG	2242	748	63	810	810	810	N/A	mA
XQZU19EG	3433	1145	96	1240	1240	1240	N/A	mA
XQ Ruggedized Zynq UltraScale+ RFSoCs
XQZU21DR	4500	770	50	320	320	320	250	mA
XQZU28DR	4500	770	50	320	320	320	250	mA
XQZU29DR	4500	1020	50	320	320	320	N/A	mA
XQZU48DR	4500	1020	50	320	320	320	250	mA
XQZU49DR	4500	1020	50	320	320	320	N/A	mA
XQZU65DR	3516	602	50	261	261	261	N/A	mA
XQZU67DR	3516	602	50	261	261	261	N/A	mA

Table 3. Power Supply Ramp Time
Symbol	Description	Min	Max	Units
T_{VCCAUX_HPIO}	Ramp time from GND to 95% of V_{CCAUX_HPIO}	0.2	40	ms
T_{VCCAUX_HDIO}	Ramp time from GND to 95% of V_{CCAUX_HDIO}	0.2	40	ms

Power Guidelines - Power Guidelines - UG584

Using LVAUX Mode in XQ Ruggedized UltraScale+ Devices for Airborne Systems Design Guide (UG584)

PL/FPGA Power-On/Off Power Supply Sequencing

Power Supply Requirements