LVAUX Mode Checklists

Use the following checklists to set up the design to support LVAUX mode.

PCB Design Checklist

V_CCAUX must be powered at 1.8V.
V_{CCAUX_HDIO} must be powered at 1.8V.
V_CCO for HD I/O banks must be powered in accordance with standard device guidance.
V_CCAUX and V_{CCAUX_HDIO} should be powered from a common supply source, although V_CCAUX can be fed separately through a current sense resistor for SEL monitoring and mitigation.
V_{CCAUX_HPIO} must be powered at 1.2V for all used and unused HP I/O pins.
V_CCO must be powered at 1.2V for all used and unused HP I/O pins.
V_{CCAUX_HPIO} and V_CCO for HP I/O banks must be shared.
For XQ UltraScale+ FPGAs only, the bank 0 voltage (V_{CCO_0}) must be 1.5V or 1.8V, and configuration is limited to the supported configuration modes listed in FPGA Configuration Modes.

DCI versions of the LVAUX I/O standards are not supported.
LVCMOS12_LVAUX only supports a drive strength of 8 mA.
SSTL12_LVAUX, DIFF_SSTL12_LVAUX, AIO_LVAUX, and DIFF_AIO_LVAUX only support the 40Ω source termination feature (OUTPUT_IMPEDANCE attribute) and on-die termination (ODT) attribute of 40Ω or 60Ω.
LVDS12_LVAUX must have differential termination turned on and set to 100Ω (attributes DIFF_TERM = TRUE and DIFF_TERM_ADV = TERM_100).
ANALOG and ANALOG_SE I/O standards are not supported in LVAUX mode HP I/O banks. (Instead, if HD I/O are available in the device, consider routing external analog inputs through an HD I/O.)

Devices operating in LVAUX mode require approximately the same amount of power as standard operating mode. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to determine the power consumption of your device.
Devices operating in LVAUX mode draw more current than standard operating mode. See Estimating Power for the methodology to calculate the current drawn from a device in LVAUX mode.

All used HP I/O pins must use an LVAUX I/O standard listed in SelectIO Resources. You cannot apply non-LVAUX I/O standards to HP I/O pins when using the device in LVAUX mode.
Design must be completed in Vivado Design Suite 2019.2 or later.
IBUF_LOW_PWR attribute on all LVAUX HP I/O pins must be set to FALSE.

DDR4 component memory is the only DDR support for PL operating in LVAUX mode, with the supported maximum speeds as identified in this document in Memory Interface Guidelines.
DDR4 memory interfaces must be generated through the IP catalog in the Vivado tools with a special LVAUX Tcl command. See Vivado Tools Requirements and Design Guidelines for more information.