AMD UltraScale+™ devices are susceptible to radiation induced upsets, as are virtually all advanced and complex semiconductor devices. The industry broadly refers to radiation effects under the umbrella term of single-event effects (SEE). For an introduction to radiation effects, and a full write-up of types of SEE and the impact to AMD devices, see Considerations Surrounding Single Event Effects in FPGAs, ASICs, and Processors (WP402). AMD proactively designs for reduction and mitigation of SEEs, with an objective to reduce the SEE rates with each successive product family.
UltraScale+ devices are built on the TSMC 16 nm FinFET+ process node. This first FinFET node for AMD has allowed for great reductions in single event upset (SEU) rates. While previous platforms were not susceptible to single-event latch-up (SEL), the UltraScale+ devices have exhibited SEL, as identified in the IEEE paper (Single Event Latch-Up: Increased Sensitivity from Planar to FinFET, J. Karp, M. J. Hart, P. Maillard, Xilinx, Inc.; G. Hellings, D. Linten, IMEC; IEEE NSREC 2017, http://ieeexplore.ieee.org/document/8141939/). This SEL rate was discovered and characterized through extensive pre-production radiation testing and characterization. While the SEL rate is significantly mitigated through silicon design enhancements, a very low rate, low current, and non-destructive or damaging SEL rate remains.
Certain classes of Aerospace & Defense (A&D) applications that are exposed to significantly higher levels of radiation, such as applications targeting commercial aircraft, might seek to assess and mitigate the remaining low-rate SEL. For applications where this is important, the AMD Defense-grade (XQ) UltraScale+ devices allow for an additional mitigation method that is not available in the AMD Commercial (XC) or AMD Automotive (XA) devices. This SEL mitigation method is achieved by using the auxiliary I/O in low-voltage (LVAUX) mode that is only available when specifying the XQ ruggedized packages. The background on UltraScale+ SEL rates and the mitigation approaches are discussed in this document along with detailed guidelines on how to design for and operate the device in the LVAUX mode.
See the Defense-Grade UltraScale Architecture Data Sheet: Overview (DS895) for available XQ UltraScale+ devices and ruggedized packages.