Decoupling Capacitors - UG584

The recommended decoupling capacitor quantities for the specific XQ ruggedized UltraScale+ device-packages in LVAUX mode are listed in the tables below. The optimized quantities of PCB decoupling capacitors assume that the voltage regulators have stable output voltages and meet the regulator manufacturer's minimum output capacitance requirements.

The assumptions used for the decoupling quantities are shown below. If any of these assumptions significantly differ from the actual design, simulations are recommended to determine the actual amount of required capacitance, which could be higher or lower. The decoupling recommendations are designed for optimal performance between roughly 100 kHz and 10–20 MHz.

Because device capacitance requirements vary with programmable logic and I/O utilization, PCB decoupling guidelines are provided on a per-device basis based on very high utilization so as to cover a majority of use cases. Resource usage consists (in part) of:

• 80% of LUTs and registers at 245 MHz and 25% toggle rate
• 80% block RAM and DSP at 491 MHz and 50% toggle rate
• 50% MMCM and 25% PLL at 500 MHz
• 25% I/O at SSTL 1.2/1.35 at 1200 MHz and 40% toggle rate
• 75% I/O at POD 1.2 at 1200 MHz DDR mode and 40% toggle rate

Different step loads are assumed for each main voltage rail. The step load is the percentage of the dynamic current that is expected to be demanded at any given switching event. The following table lists the step load percentage used when calculating device capacitance requirements.

The slew rate of the switching event is dependent on the design, and can be estimated to be between 1 ns and 100 ns (or longer). Smaller current designs generally have faster current slew rates, while larger designs tend to have slower slew rates. A general rule of thumb for high-current designs can be considered to be 0.25 ns per amp (or 4 A/ns) of step current. The Xilinx Power Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) is used to estimate the current on each power rail.

See the Recommended Operating Conditions in this document for the operating range of the V_{CCAUX_HPIO} supply. Otherwise, see the Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922), Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923), Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925), or Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926) for the operating range for all other power rails. The PCB designer should ensure that the AC ripple plus the DC tolerance of the voltage regulator do not exceed the operating range.

The capacitor numbers shown in this user guide are based on the following assumptions:

• VCCINT operating range from the data sheet = 3%
• Assumed DC tolerance = 1%
• Therefore, allowable AC ripple = 3% – 1% = 2%

The target impedance is calculated using the 2% AC ripple along with the current estimates from XPE for the above resource utilization to arrive at the capacitor recommendations. The equation for target impedance is:

Ztarget = VoltageRailValue x (% Ripple/100) / StepLoadCurrent

V_CCINT, V_CCAUX, and V_CCBRAM capacitors are listed as the quantity per device, while V_CCO capacitors are listed as the quantity per I/O bank. Device performance at full utilization is equivalent across all devices when using these recommended networks.

The decoupling capacitor tables below do not provide the decoupling networks required for the GTY or GTH transceiver power supplies. For this information, refer to the UltraScale Architecture GTY Transceivers User Guide (UG578) or UltraScale Architecture GTH Transceivers User Guide (UG576).

Recommended decoupling capacitor quantities in the tables below are based on the following capacitors and capacitor placement.

The following are recommended decoupling capacitor quantities based on the above capacitors and assumptions.