Only the DDR4 SDRAM memory interface is
supported with the LVAUX I/O standards. The SFRA484 package does not support PL memory
interfaces. The following steps are used to enable LVAUX for DDR4 on the PL side using
the Vivado Design Suite:
- Using the Design Flow Steps described in UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP Product Guide (PG150), generate the IP for DDR4 SDRAM (MIG).
- In the Generate Output Products dialog, do not select Generate, instead select Skip. By clicking Generate, RTL is generated and the Tcl command in the next step is ignored.
- In the Tcl console, run the following command:
set_property -dict [list CONFIG.C0.DDR4_Enable_LVAUX {true}] [get_ips <ddr4_ip_name>] - Right-click the DDR4 IP file in the Design Sources folder and select Generate Output Products. Click Generate to create the output files. The I/O standard changes made using the Tcl command are applied in the generated files.
- Confirm that the DDR4 ports are set to the LVAUX I/O standards in the
following file.
<project_name>.srcs\sources_1\ip\<ddr4_ip_name>\par\<ddr4_ip_name>.xdc