Using LVAUX Mode in XQ Ruggedized UltraScale+ Devices for Airborne Systems Design Guide (UG584)

Document ID: UG584
Release Date: 2024-05-03
Revision: 1.1 English

Introduction
SEL Rate and Impact Assessment
UltraScale+ Device SEL
SEL Impact
SEL Mitigation Options Overview
Current Monitoring
Decision Tree
LVAUX Mode Overview
SelectIO Resources
Supply Voltages for SelectIO Pins
Special Considerations for XQ Ruggedized FPGAs
Summary of LVAUX Mode versus Standard Operating Mode
LVAUX Mode Checklists
Hardware Requirements and Guidelines for LVAUX Mode
DC and AC Switching Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Power Guidelines
DC I/O Levels
IOB High Performance Switching Characteristics
I/O Guidelines
LVCMOS12_LVAUX
SSTL12_LVAUX and DIFF_SSTL12_LVAUX
AIO12_LVAUX and DIFF_AIO12_LVAUX
LVDS12_LVAUX
MIPI_DPHY_LVAUX
Rules for Combining I/O Standards in the Same Bank
Termination Options for Simultaneous Switching Noise Analysis
Packaging and Pinouts
PCB Design Guidelines
Decoupling Capacitors
Estimating Power
Methodology
Vivado Tools Requirements and Design Guidelines
DDR4 SDRAM Memory Interface Generator
I/O Interface Attributes and Constraints
Memory Interface Guidelines
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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