UltraScale Architecture PCB Design User Guide (UG583) - Describes strategies for PCB and interface-level designs using AMD UltraScale™ and AMD UltraScale+™ devices. - UG583
Document_ID
UG583
Release_Date
2025-12-23
Revision
1.29 English
Power Distribution System in UltraScale Devices
Introduction to the UltraScale Architecture
Introduction
PCB Decoupling Capacitors
VCC_PSDDR_PLL Supply
Video Codec Unit (MPSoC EV Devices Only)
VCCINT_VCU Decoupling Capacitors
VCCINT_VCU Plane Design and Power Delivery
Transceiver PCB Routing Guidelines
Power Supply Consolidation Solutions for Zynq UltraScale+ MPSoCs
Power Supply Consolidation Solutions
Always On: Optimized for Cost (-1 and -2 Devices)
Always On: Optimized for Power and/or Efficiency (-1L and -2L Devices)
Always On: Optimized for PL Performance (-3 Devices)
Full Power Management Flexibility (All Speed Grades/Devices)
PCB Guidelines for Memory Interfaces in Kintex UltraScale+, Virtex UltraScale+, and Zynq UltraScale+ Devices
Overview
Reference Stackup
General Memory Routing Guidelines
Adjusting for Different Stack-Ups
Dielectric Material
Trace Width
Layer Height
Base Copper Weight
Example of Tuning Design Parameters to Meet Impedance Targets
PCB Guidelines for DDR4 SDRAM (PL and PS)
Overview
DDR4 SDRAM Interface Signal Description
Fly-by and Clamshell Topologies
Using Address Mirroring to Ease Clamshell Routing
ECC Connection Rules for DDR4 SDRAM
Routing Rule Changes for Thicker Printed Circuit Boards
Topology and Routing Guidelines for DDR4 SDRAM
DDR4 SDRAM Address, Command, and Control Fly-by and Clamshell Topologies
reset_n
alert_n
DDR4 SDRAM Clock Fly-By and Clamshell Termination
DDR4 SDRAM Data Signals Point-to-Point for Fly-by and Clamshell Configurations
DDR4 SDRAM Routing Constraints
PCB Guidelines for DDR3/3L SDRAM (PL and PS)
Overview
DDR3 SDRAM Interface Signal Description
Topology and Routing Guidelines for DDR3 SDRAM
DDR3 SDRAM Address, Command, and Control Fly-by Termination
reset_n
DDR3 SDRAM Clock Fly-by Termination
DDR3 SDRAM Data Signals Point-to-Point
DDR3 SDRAM Routing Constraints
DDR3/DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Guidelines (PL and PS)
DDR3/DDR4 DIMM Clock Point-to-Point Routing
DDR3/DDR4 DIMM Control, Command, and Address Routing
reset_n
DDR3/DDR4 DIMM Data (DQ and DQS) Routing
DDR3 UDIMM/RDIMM/SODIMM/LRDIMM Routing Constraints
DDR4 UDIMM/RDIMM/SODIMM/LRDIMM Routing Constraints
PCB Guidelines for LPDDR4 Memories without ECC (PS)
Overview
LPDDR4 x32 without ECC Memory Interface Signals and Connections
Signals and Connections for x32 Dual Channel LPDDR4 SDP without ECC
Signals and Connections for x32 Dual Channel LPDDR4 DDP without ECC
LPDDR4 Address Copy
LPDDR4 Interface without ECC Topology and Routing Guidelines
LPDDR4 Interface without ECC Address/Command and Control Routing
LPDDR4 Interface without ECC Chip Select Routing
LPDDR4 without ECC Clock Enable Routing
LPDDR4 without ECC CK and DQS Differential Point-to-Point Routing
LPDDR4 without ECC Data (DQ and DM) Point-to-Point Routing
LPDDR4 without ECC Length and Skew Constraints
PCB Guidelines for LPDDR4 Memories with ECC (PS)
Overview
LPDDR4 x32 with ECC Memory Interface Signals and Connections
LPDDR4 Address Copy
LPDDR4 with ECC Topology and Routing Guidelines
LPDDR4 with ECC Address/Command and Control Routing (CA_A)
LPDDR4 with ECC Address/Command and Control Routing (CA_B)
LPDDR4 with ECC Chip Select Routing
LPDDR4 with ECC Clock Enable Routing
LPDDR4 with ECC CK0 Differential Point-to-Point Routing
LPDDR4 with ECC CK1 Differential Fly-by Routing
LPDDR4 with ECC Data (DQ) Point-to-Point Routing
LPDDR4 with ECC DQS Differential Point-to-Point Routing
LPDDR4 with ECC Length and Skew Constraints
PCB Routing Guidelines for LPDDR4 Memories in High-Density Interconnect Boards
PCB Guidelines for LPDDR3 SDRAM (PL and PS)
Overview
LPDDR3 SDRAM Interface Signal Description
LPDDR3 Address Copy
VREFCA and VREFDQ
Design Example for x32 and x64 LPDDR3 SDRAM
Topology and Routing Guidelines for LPDDR3 SDRAM
LPDDR3 SDRAM Clk Point-to-Point Termination
LPDDR3 SDRAM Address, Command, and Control Point-to-Point Termination
LPDDR3 SDRAM Control Fly-by Termination for x64 Two-SDRAM System
LPDDR3 SDRAM Data Signals Point-to-Point
LPDDR3 SDRAM Routing Constraints
PCB Guidelines for RLDRAM 3 Memory
Overview
RLDRAM 3 Memory Interface Signal Description
RLDRAM 3 Memory Topology and Routing Guidelines for Clamshell and Fly-by Configurations
RLDRAM 3 Memory Clamshell Configuration with Width Expansion
RLDRAM 3 Memory Fly-by Configuration with Width Expansion
RLDRAM 3 Memory Address and Command Clamshell Routing and Termination
RLDRAM 3 Memory Address and Command Fly-by Routing and Termination
RLDRAM 3 Memory CK_P/N Clamshell Routing
RLDRAM 3 Memory CK_P/N Fly-by Routing
RLDRAM 3 Memory DK_P/N and QK_P/N Differential Point-to-Point Routing
RLDRAM 3 Memory Data Signals Point-to-Point
RLDRAM 3 Memory Routing Constraints
PCB Guidelines for QDR II+ SRAM
Overview
QDR II+ SRAM Interface Signal Description
Design Example for Dual QDR II+ SRAM Devices
QDR II+ SRAM Topology and Routing Guidelines for Fly-by Configuration
QDR II+ SRAM Address and Command Fly-by Routing and Termination
Additional QDR II+ SRAM Routing Guidelines
QDR II+ SRAM Topology and Routing Guidelines for T-Branch Configuration
QDR II+ SRAM Clock (K, K_B, and BWS) T-Branch Routing and Termination
QDR II+ SRAM Clock and Data Signals (d/k/k_b) Point-to-Point Routing
QDR II+ SRAM Clock and Data Signals (q/cq/cq_b) Point-to-Point Routing
QDR II+ SRAM Routing Constraints
PCB Guidelines for QDR-IV SRAM
Overview
QDR-IV SRAM Interface Signal Description
Design Example for Dual QDR-IV SRAM Devices
QDR-IV Topology and Routing Guidelines
QDR-IV SRAM DQ/Address/Command Routing
QDR-IV SRAM CK/DK/QK Routing and Termination
QDR-IV SRAM Routing Constraints
PCB Guidelines for Memory Interfaces in Spartan UltraScale+ Devices
Overview
Required Memory Routing Guidelines for All Interfaces
Reference Material Specifications
Adjusting for Different Stack-Ups
PCB Guidelines for DDR4 SDRAM
Overview
DDR4 SDRAM Interface Signal Description
Fly-by and Clamshell Topologies
Using Address Mirroring to Ease Clamshell Routing
ECC Connection Rules for DDR4 SDRAM
Routing Rule Changes for Thicker Printed Circuit Boards
Topology and Routing Guidelines for DDR4 SDRAM
DDR4 SDRAM Address, Command, and Control Fly-by and Clamshell Topologies
reset_n
alert_n
DDR4 SDRAM Clock Fly-By and Clamshell Termination
DDR4 SDRAM Data Signals Point-to-Point for Fly-by and Clamshell Configurations
DDR4 SDRAM Routing Constraints
PCB Routing Guidelines for LPDDR5 Interfaces
Signals and Connections for LPDDR5 Interfaces
Physical Design Rules for LPDDR5 Signals
Timing Constraint Rules for LPDDR5 Signals
PCB Routing Guidelines for LPDDR4x Interfaces
Signals and Connections for LPDDR4x Interfaces
Physical Design Rules for LPDDR4x Signals
Timing Constraint Rules for LPDDR4x Signals
PCB Guidelines for Zynq UltraScale+ RFSoCs
PDN Guidelines for RFSoC Digital Power Rails
Power Delivery to the Programmable Logic Voltage Rails
VCCINT, VCCINT_IO, and VCCBRAM Tied Together (-1E, -1I, -2I, -2E)
Separate VCCINT and VCCBRAM/VCCINT_IO (-1LI, -2LI, -2LE)
VCCSDFEC
VCCSDFEC and Migration
PCB Decoupling Recommendations
Power Delivery to the PS-GTR and GTY Transceivers
ADC and DAC PCB Guidelines
Zynq UltraScale+ RFSoC Device Organization and PCB Design Overview
Analog Ground to Digital Ground Connection
Choosing the Appropriate Balun
Recommended Clocking Options
RF PLL Placement and Routing
Analog and Clock Pair Routing
Trace Routing Impedance Recommendation
AC/DC Coupling Guidelines
Isolation Recommendations
P and N Skew Specifications
Insertion Loss Recommendations
Return Loss Recommendations
Pi Network for Improved Return Loss in Gen 1 Devices (XCZU25DR/ XCZU27DR/XCZU28DR/XCZU29DR)
SYSREF
Calibration Resistors
Sample Stackup
PCB Stackup
Layer 1 (Top Layer) in BGA Area for DACs/ADCs
Layer 2 in BGA Area for DACs/ADCs
Layer 3 in BGA Area for DACs/ADCs
Layer 4 in BGA Area for DACs/ADCs
Layer 5 in BGA Area for DACs/ADCs
Layer 6 for Clock Routes
Guard Traces along the Length of the Trace Routes
Neck Down Trace
Layer 2 Routing for AC Coupling Capacitor Inputs and Outputs
Layer 4 Routing for AC Coupling Capacitor Inputs and Outputs
Layer 2 Between AC Capacitors and Baluns
Layer 4 Between AC Capacitors and Baluns
Unused ADC & DAC Pins
Power Regulation and Decoupling for ADC and DAC Supplies
Recommended Linear Regulators
ADC and DAC Voltage Supply Specifications
Decoupling Capacitor Antipad to Reduce Insertion and Return Loss
Voltage Sensing
Unused ADC and DAC Power Pins
Powering RFSoCs with Switch Regulators
Power Delivery Network Design for Time Division Duplex
PCB Guidelines for the PS Interface in the Zynq UltraScale+ MPSoC
Boot Mode
CAN
DisplayPort
eMMC
Standard and High-Speed SDR Interfaces
HS200 (200 MHz) and High-Speed DDR Interfaces
Ethernet MAC RGMII
Ethernet MAC SGMII
I2C
JTAG
NAND Memory Controller
SDR Mode
DDR Mode (100 MHz)
PCIe
PS_INIT_B, PS_PROG_B, and PS_DONE
PS Reference Clock
PS Reset (External System Reset and POR Reset)
QSPI
Real-Time Clock
SATA
SD/SDIO
SPI
Trace Port Interface Unit
Triple Time Counter
UART
USB 2.0
ULPI Interface (60 MHz)
USB 3.0
Watchdog Timer
PS-GTR Transceiver Interfaces
Pin Description and Design Guidelines
Reference Clock
Reference Clock Interface
AC Coupled Reference Clock
Unused Reference Clocks
Reference Clock Power
Power Supply Noise
PCB Design Checklist
PCB Routing Guidelines for MIPI D-PHY
Migration between UltraScale Devices and Packages
UltraScale Device Migration Checklist
1. Footprint Compatibility between Packages
Examples
2. Package Dimensions
Example
3. I/O Bank and Transceiver Quad Numbers
Example: Planning Ahead for Bank Number Changes
4. HP/HR Migration
5. GTH/GTY Transceiver Migration
Example
MGTRREF and MGTAVTTRCAL
6. SLR Migration
Example
7. Monolithic to Stacked Silicon Migration
Example: Migration from Monolithic XCKU060 to SSI XCKU115 in A1517 Package
8. Memory Interface Migration
Example
9. DCI Cascade and Internal VREF Features
Example
10. System Monitor
Example
11. Decoupling Capacitors
Example
12. PCI Express Migration
13. Integrated 100G Ethernet Migration
14. Interlaken Migration
15. Power Supplies and Thermal Considerations
16. Pin Flight Times across Packages
Example
Migration between UltraScale and UltraScale+ FPGAs
UltraScale+ FPGA Migration Checklist
1. Package Migration from UltraScale to UltraScale+ FPGAs
2. Voltage Differences between UltraScale to UltraScale+ FPGAs
3. Power Supply Voltage Levels and VCCINT_IO Connection
4. I/O Changes from UltraScale to UltraScale+ FPGAs
5. Transceiver Changes from UltraScale FPGAs to UltraScale+ FPGAs
6. Configuration
7. Memory Interface PCB Routing
8. SMBAlert
9. Block RAM
10. ESD Requirements
11. PCI Express
12. Migration Examples
Example One: VU125 to VU7P in C2104 Package
Example Two: VU190 to VU13P in A2577 Package
13. Migration Scenarios
Migration between Zynq UltraScale+ MPSoCs and Packages
Zynq UltraScale+ MPSoC Migration Checklist
1. Footprint Compatibility between Packages
Example 1
Example 2
Example 3
2. I/O Bank and Transceiver Quad Numbers
Example: Planning Ahead for Bank Number and Location Changes
3. Power Supply Differences across Speed Grades and Temperature Grades
4. -3 Speed Migration
5. VCU Migration
Example: Schematic/PCB Options to Enable VCU Migration from EV to CG/EG Devices
6. GPU Migration
7. Decoupling Capacitors
8. PCI Express Migration
9. Integrated 100G Ethernet Migration
10. Interlaken Migration
11. Power Supplies and Thermal Considerations
12. Pin Flight Times across Packages
Example 1: Obtaining Pin Flight Times During I/O Planning
Example 2: Obtaining Pin Flight Times after Synthesis
Using the Enable Migration Feature for DDR4 Memory Designs (Vivado Tools 2016.3)
Migration between Virtex UltraScale+ VU13P Devices and VU27P/VU29P Devices
Power Supply Differences
New VCCINT_GT Rail
VRM Sizing and Decoupling Capacitor Quantities
VRM Sizing
Decoupling Capacitor Quantities
Package Height and Thermal Design Differences
Package Height
Thermal Design
Package Flight Time Differences
Bonded/Unbonded Bank/Quad Differences
CMAC/PCIe Location Differences
GTY/GTM Channel and Clock Mapping Differences
100G Ethernet Layout Guidelines
SelectIO Signaling
Interface Types
Single-Ended versus Differential Interfaces
SDR versus DDR Interfaces
Single-Ended Signaling
Modes and Attributes
Input Thresholds
Topographies and Termination
Unidirectional Topographies and Termination
Unidirectional Point-to-Point Topographies
Unidirectional Multi-Drop Topographies
Bidirectional Topography and Termination
Bidirectional Multi-Point Topographies
PCB Technology Basics
Introduction
PCB Structures
Traces
Planes
Vias
Pads and Antipads
Lands
Dimensions
Basic PDS Principles
Noise Limits
Role of Inductance
Capacitor Parasitic Inductance
PCB Current Path Inductance
Capacitor Mounting Inductance
Plane Inductance
FPGA Mounting Inductance
PCB Stackup and Layer Order
Capacitor Effective Frequency
Capacitor Anti-Resonance
Capacitor Placement Background
VREF Stabilization Capacitors
Power Supply Consolidation
Unconnected VCCO Pins
Transmission Lines
Return Currents
PCB Materials and Traces
How Fast is Fast?
Dielectric Losses
Relative Permittivity
Loss Tangent
Skin Effect and Resistive Losses
Choosing the Substrate Material
Traces
Trace Geometry
Trace Characteristic Impedance Design for High-Speed Transceivers
Trace Routing
Plane Splits
Return Currents
Simulating Lossy Transmission Lines
Cable
Connectors
Skew Between Conductors
Simulation Methods
PDS Measurements
Noise Magnitude Measurement
Noise Spectrum Measurements
Optimum Decoupling Network Design
Troubleshooting
Possibility 1: Excessive Noise from Other Devices on the PCB
Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces
Possibility 3: I/O Signals in PCB are Stronger Than Necessary
Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths
Design of Transitions for High-Speed Signals
Excess Capacitance and Inductance
Time Domain Reflectometry
BGA Package
SMT Pads
Differential Vias
P/N Crossover Vias
SMA Connectors
Backplane Connectors
Microstrip/Stripline Bends
Maximum Current Draw for VCCINT in UltraScale+ Devices
Memory Derating Tables
Material Properties and Insertion Losses
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices