Pin Definitions

User I/O Pins

IO_L[ 1 to 24 ][P or N]_T[ 0 to 3 ] [ U or L ]_N[ 0 to 12 ]_ [multi-function]_[bank number] or

IO_T[ 0 to 3 ][ U or L ]_N[ 0 to 12 ]_[multi-function]_[bank number]

Multi-
function

Input/
Output

Most user I/O pins are capable of differential signaling and can be implemented as pairs. Each user I/O pin name consists of several indicator labels, where:

• IO indicates a user I/O pin.

• L[ 1 to 24 ] indicates a unique differential pair with P (positive) and N (negative) sides. User I/O pins without the L indicator are single-ended.

• T[ 0 to 3 ][ U or L ] indicates the assigned byte group and nibble location (upper or lower portion) within that group for the pin.

• N[ 0 to 12 ] the number of the I/O within its byte group.

• [ multi-function ] indicates any other functions that the pin can provide. If not used for this function, the pin can be a user I/O.

• [ bank number ] indicates the assigned bank for the user I/O pin.

GC or HDGC

Multi-
function

Input/
Output

Four global clock (GC) pin pairs are in each bank. HDGC pins have direct access to the global clock buffers. GC pins have direct access to the global clock buffers, MMCMs, and PLLs that are in the clock management tile (CMT) adjacent to the same I/O bank. GC and HDGC inputs provide dedicated, high-speed access to the internal global and regional clock resources. GC and HDGC inputs use dedicated routing and must be used for clock inputs where the timing of various clocking features is imperative. GC or HDGC pins can be treated as user I/O when not used as input clocks.
Up-to-date information about designing with the GC
(or HDGC) pin is available in the UltraScale Architecture Clocking Resources User Guide ( UG572 ).

VRP ⁽¹⁾

Multi-
function

N/A

This pin is for the DCI voltage reference resistor of P transistor (per bank, to be pulled Low with a reference resistor).

DBC
QBC

Multi-
function

Input

Byte lane clock (DBC and QBC) input pin pairs are clock inputs directly driving source synchronous clocks to the bit slices in the I/O banks. In memory applications, these are also known as DQS. For more information, consult the UltraScale Architecture SelectIO Resources User Guide ( UG571 ).

PERSTN[ 0 to 1 ]

Multi-
function

Input

Default reset pin locations for the integrated block for PCI Express.

User I/O Multi-Function Configuration Pins

For further descriptions, including configuration modes and recommended external pull-up/pull-down resistors, see the UltraScale Architecture Configuration User Guide ( UG570 ).

EMCCLK

Multi-
function

Input

External master configuration clock.

DOUT_CSO_B

Multi-
function

Output

Data output for serial daisy-chaining or active-Low chip-select output for SelectMAP daisy-chaining.

D[ 04 to 31 ]

Multi-
function

Bidirectional

Configuration data pins.

A[ 00 to 28 ]

Multi-
function

Output

Address output.

CSI_ADV_B

Multi-
function

Input or Output

Active-Low chip-select input or address valid output.

FOE_B

Multi-
function

Output

Active-Low flash output enable.

FWE_FCS2_B

Multi-
function

Output

Active-Low flash write-enable for BPI flash or flash chip-select for second SPI (x8) flash.

RS[ 0 to 1 ]

Multi-
function

Output

Revision select outputs.

Dedicated (Bank 0) Configuration Pins ⁽²⁾

For more information see the UltraScale Architecture Configuration User Guide ( UG570 ).

M[ 0 to 2 ]_0

Dedicated

Input

Configuration mode selection.

INIT_B_0

Dedicated

Bidirectional
(open-drain)

Active-Low initialization

CFGBVS_0

Dedicated

Input

Bank 0 and bank 65 voltage select. This pin determines the I/O voltage operating range and voltage tolerance for the dedicated configuration bank 0 and multi-function bank 65. Connect CFGBVS High or Low per the bank voltage requirements.

• V _{CCO_0} = 2.5V or 3.3V, tie CFGBVS High (connect to V _{CCO_0} ).

• V _{CCO_0} = 1.5V or 1.8V, tie CFGBVS Low (connect to GND)

CAUTION! To avoid device damage, this pin must be connected correctly to either V _{CCO_0} or GND.

PUDC_B_0

Dedicated

Input

Active-Low input enables internal pull-ups during configuration on all SelectIO pins:
0 = Weak preconfiguration I/O pull-up resistors enabled.

1 = Weak preconfiguration I/O pull-up resistors disabled.

POR_OVERRIDE

Dedicated

Input

All configuration modes

Power-on reset delay override.

CAUTION! Do not allow this pin to float before and during configuration. This pin must be tied to V _CCINT or GND. Do not connect to V _{CCO_0} .

Information about designing with the POR_OVERRIDE pin is available in the UltraScale Architecture Configuration User Guide ( UG570 ).

DONE_0

Dedicated

Bidirectional

Active-High, DONE indicates successful completion of configuration.

PROGRAM_B_0

Dedicated

Input

Active Low, asynchronous reset to configuration logic.

TDO_0

Dedicated

Output

JTAG test data output.

TDI_0

Dedicated

Input

JTAG test data input.

RDWR_FCS_B_0

Dedicated

Input/
Output

Input control signal for SelectMAP data bus direction: High for reading or Low for writing configuration data.

Or, active-Low flash chip-select output.

TMS_0

Dedicated

Input

JTAG test mode data select.

TCK_0

Dedicated

Input

JTAG test clock

CCLK_0

Dedicated

Input/
Output

Configuration clock. Output in Master mode or input in Slave mode.

D00_MOSI_0

Dedicated

Bidirectional

Data Bit 0 or SPI master-output

D01_DIN_0

Dedicated

Bidirectional

Data Bit 1 or serial mode data input

D02_0

Dedicated

Bidirectional

Data Bit 2

D03_0

Dedicated

Bidirectional

Data Bit 3

Other Dedicated Pins

DXN

Dedicated

N/A

Temperature-sensing diode pins (Anode: DXP; Cathode: DXN). The thermal diode is accessed by using the DXP and DXN pins in bank 0. When not used, tie to GND.

To use the thermal diode an appropriate external thermal monitoring IC must be added. Consult the external thermal monitoring IC data sheet for usage guidelines.

DXP

System Monitor Pins ⁽³⁾

AD[0 to 15][P or N]

Multi-
function

Input

System Monitor differential auxiliary analog inputs 0–15.

VCCADC

Dedicated

N/A

System Monitor analog positive supply voltage.

GNDADC

Dedicated

N/A

System Monitor analog ground reference.

VREFP

Dedicated

N/A

Voltage reference input.

VREFN

Dedicated

N/A

Voltage reference GND.

VP

Dedicated

Input

System Monitor dedicated differential analog input (positive side).

VN

Dedicated

Input

System Monitor dedicated differential analog input (negative side).

I2C_SCLK

Multi-
function

Bidirectional

I2C serial clock. Directly connected to the System Monitor DRP interface for I2C operation configuration.

IMPORTANT: Because the SYSMON I2C interface is active after power-on, this pin should only be used for I2C access until after configuration.

I2C_SDA

Multi-
function

Bidirectional

I2C serial data line. Directly connected to the System Monitor DRP interface for I2C operation configuration.

IMPORTANT: Because the SYSMON I2C interface is active after power-on, this pin should only be used for I2C access until after configuration.

SMBALERT

Multi-
function

Bidirectional

Optional PMBus alert, interrupt signal. When Low, indicates a system fault that must be cleared using PMBus commands. Connect to SMBALERT_TS.

For more information, see the UltraScale Architecture System Monitor User Guide ( UG580 ).

IMPORTANT: By default, the PMBus is active prior to configuration. Only use as a multi-functional I/O pin in designs that can tolerated this pin being driven prior to configuration.

This pin is present on Artix UltraScale+ , Kintex UltraScale+ , and Virtex UltraScale+ devices.

Power/Ground Pins

For more information on voltage specifications see the UltraScale Device Data Sheets .

GND

Dedicated

N/A

Ground.

VCCINT

Dedicated

N/A

Power-supply pins for the internal logic.

VCCINT_IO

Dedicated

N/A

Power-supply pins for the I/O banks. For Kintex and UltraScale Architecture PCB and Pin Planning User Guide devices, connect VCCINT_IO to VCCINT. For Kintex and Virtex UltraScale+ devices, connect VCCINT_IO to VCCBRAM. Both migration and lower voltage differences (-1LI and -2LE at 0.72V) are discussed in the UltraScale Architecture PCB Design Guide ( UG583 ). See the connection matrix in the Power Supply Voltage Levels and VCCINT_IO Connection section.

VCCINT_GT_[ L or R ]

Dedicated

N/A

GTM core power-supply pins.

VCCAUX

Dedicated

N/A

Power-supply pins for auxiliary circuits.

VCCAUX_IO

Dedicated

N/A

Auxiliary p ower-supply pins for the I/O banks. VCCAUX_IO must be connected to VCCAUX on the board.

Note: Package files for XQ ruggedized Kintex and Virtex UltraScale+ devices (for example: FFRB676) have unique pin names for VCCAUX_HPIO and VCCAUX_HDIO. These pins can be connected to a common VCCAUX_IO supply.

VCCIO_HBM_[HBM bank number]

Dedicated

N/A

HBM component I/O power supply (VDDQ)

VCC_HBM_[HBM bank number]

Dedicated

N/A

HBM component core power supply (VDDC)

VCCAUX_HBM_[HBM bank number]

Dedicated

N/A

HBM component word line voltage pump (VPP)

VCCBRAM

Dedicated

N/A

Block RAM power supply pins.

VBATT

Dedicated

N/A

Decryptor key memory backup supply; this pin should be tied to the appropriate V _CC or GND when not used.

VCCO_[bank number] ⁽⁴⁾

Dedicated

N/A

Power-supply pins for the output drivers (per bank).

VREF_[bank number]

Dedicated

N/A

These are input threshold voltage pins.

RSVDGND

Dedicated

N/A

Reserved pins—must be tied to GND.
These pins are present on Artix UltraScale+ , Kintex UltraScale+ , and Virtex UltraScale+ devices.

TIP: In footprint compatible devices, this pin can be labeled differently and serve different purposes. When planning migration between devices, include the functionality between all footprint compatible devices.

RSVD

Dedicated

N/A

Reserved pins—leave floating.

TIP: In footprint compatible devices, this pin can be labeled differently and serve different purposes. When planning migration between devices, include the functionality between all footprint compatible devices.

Multi-gigabit Serial Transceiver Pins (GTHE3 and GTYE3)

For more information on the GTH and GTY transceivers see the UltraScale Architecture GTH Transceivers User Guide ( UG576 ) or UltraScale Architecture GTY Transceivers User Guide ( UG578 ).

MGTHRX[P or N][0 to 3]
_[GT quad number]

Dedicated

Input

Differential receive port GTH Quad.

MGTHTX[P or N][0 to 3]
_[GT quad number]

Dedicated

Output

Differential transmit port GTH Quad.

MGTYRX[P or N][0 to 3]
_[GT quad number]

Dedicated

Input

Differential receive port GTY Quad.

MGTYTX[P or N][0 to 3]
_[GT quad number]

Dedicated

Output

Differential transmit port GTY Quad.

MGTYRX[P or N][0 to 3]
_[GT dual number]

Dedicated

Input

Differential receive port GTM Dual.

MGTYTX[P or N][0 to 3]
_[GT dual number]

Dedicated

Output

Differential transmit port GTM Dual.

MGTAVCC_[L or R]
[N, UC, C, LC, or S] ⁽⁵⁾

Dedicated

Input

Analog power-supply pin for the receiver and transmitter internal circuits.

MGTAVTT_[L or R]
[N, UC, C, LC, or S] ⁽⁵⁾

Dedicated

Input

Analog power-supply pin for the transmit driver.

MGTVCCAUX_[L or R]
[N, UC, C, LC, or S] ⁽⁵⁾

Dedicated

Input

Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers.

MGTREFCLK[0 or 1]
[P or N]

Dedicated

Input

Differential reference clock for the transceivers.

MGTAVTTRCAL_[L or R]
[N, UC, C, LC, or S] ⁽⁵⁾

Dedicated

N/A

Precision reference resistor pin for internal calibration termination.

MGTRREF_[L or R]
[N, UC, C, LC, or S] ⁽⁵⁾

Dedicated

Input

Precision reference resistor pin for internal calibration termination.

Notes:

1. See the DCI sections in UltraScale Architecture SelectIO Resources User Guide ( UG571 ) for more information on the VRP pins.

2. All dedicated configuration pins are powered by V _{CCO_0} .

3. See the UltraScale Architecture System Monitor User Guide ( UG580 ) for the default connections required to support on-chip monitoring.

4. V _CCO pins in unbonded banks must be connected to the V _CCO for that bank (for package migration). Do NOT connect unbonded V _CCO pins to different supplies. Without a package migration requirement, V _CCO pins in unbonded banks can be tied to a common supply (V _CCO or GND).

5. L (left) or R (right) plus N (north), UC (upper center), C (center), LC (lower center), and S (south) signify the GT transceiver quad power supply groups. For example, RUC signifies the right-upper-center power supply group and LLC signifies the left-lower-center power supply group in the FLGA2577 package.