This section describes the packages and pinouts for the UltraScale architecture-based FPGAs in various organic flip-chip 0.8 mm and 1.0 mm pitch BGA packages.
• Kintex UltraScale , Kintex UltraScale+ , and Artix UltraScale+ devices are offered in low-cost, space-saving flip-chip and bare-die flip-chip packages that are optimally designed for high performance-to-price ratio.
• Virtex UltraScale and Virtex UltraScale+ devices are offered exclusively in high performance flip-chip BGA packages that are optimally designed for highest system capacity, bandwidth and signal performance. Package inductance is minimized as a result of optimal placement and even distribution as well as an increased number of power and GND pins.
• Zynq UltraScale+ MPSoCs are further described in the Zynq UltraScale+ MPSoC Packaging and Pinouts User Guide ( UG1075 ).
IMPORTANT: Many of the standard packages for commercial (XC) devices are lead-free (signified by an additional V in the package name). All of the UltraScale or UltraScale+ devices supported in a particular package are footprint compatible. Each device is split into I/O banks to allow for flexibility in the choice of I/O standards. See the UltraScale Architecture SelectIO Resources User Guide ( UG571 ).
UltraScale and UltraScale+ device’s flip-chip assembly materials are manufactured using ultra-low alpha (ULA) materials defined as <0.002 cph/cm 2 or materials that emit less than 0.002 alpha-particles per square centimeter per hour.