• Each user I/O bank has a total of 52 I/Os where 48 can be used as differential (24 differential pairs) or single-ended I/Os. The remaining four function only as single-ended I/Os. All 52 pads of a bank are not always bonded out to pins.
• A limited number of banks have fewer than 52 SelectIO pins. These banks are labeled as partial.
• Adjacent to each bank is a physical layer (PHY) containing a CMT and other clock resources.
• Adjacent to each bank and PHY is a tile of logic resources that makes up a clock region.
• Banks are arranged in columns and separated into rows which are pitch-matched with adjacent PHY, clock regions, and GT blocks.
• An alphabetic designator is shown in each bank. Each letter corresponds to the columns in Table: I/O Bank Migration: HP I/O Banks are Unshaded, HR I/O Banks are in Gray, and HD I/O Banks are in Dark Gray(1) and Table: Transceiver Quad Migration (GTH Quads are White, GTY Quads are Gray, GTM Duals are Dark Gray) .