The packaging and pinout specifications for UltraScale architecture-based FPGAs differ from past generations, including the 7 series devices. These details are outlined in this section.
• All packages are constructed on organic laminate substrates.
• Many of the package and die components, including flip-chip solder bumps, are lead-free. The FLGx devices have lead in their bumps.
• Package names contain a single-character alphabetic designator followed by the exact number of pins found on the package.
• VCCAUX_IO pins are not divided into bank groups. VCCAUX_IO must be connected to VCCAUX at the board level.
• Internal logic is separated from I/O logic by the addition of the VCCINT_IO power pins. VCCINT_IO must be connected to VCCINT at the board level.
• Groups of gigabit serial transceiver (GT) power pins are separated by column for each column of GT Quads/Duals.
• Standard I/O banks each have a total of 52 SelectIO ™ pins, optionally configurable as up to 24 differential pairs.
• Each bank has one dedicated VREF pin. These pins cannot be used as user I/Os.
• Four differential clock pin pairs per bank (two per 26-pin bank) consist of a single type of global clock (GC) input.
• Four memory byte groups per I/O bank (two per 26-pin bank) are each separated into an upper and a lower memory byte group.
• All configuration pins are located in bank 0 and bank 65.
• A POR_OVERRIDE pin is used to override the default power-on-reset delay. See Table: Pin Definitions .