Carry Logic - Carry Logic - UG574

UltraScale Architecture Configurable Logic Block User Guide (UG574)

Document ID
UG574
Release Date
2025-01-22
Revision
1.6 English

In addition to function generators, dedicated fast lookahead carry logic is provided to perform fast arithmetic addition and subtraction. A CLB slice has a single carry chain, as shown in the following figure. The carry chains are cascaded to form wider add/subtract logic.

Figure 1. Fast Carry Logic Path and Associated Elements

The carry chain runs upward and has a height of eight bits per CLB slice. The carry initialize input CYINIT is used to select the first bit in a carry chain. The value for this input is either 0 (for add), 1 (for subtract), or AX input (for the dynamic first carry bit). The carry initialization function is available both at the beginning of the chain at the bottom of the CLB slice, and at the mid-point, for splitting the slice into two 4-bit carry blocks. Dedicated connections cascade a carry from the COUT pin of one slice to the CIN pin of the slice above. For each bit, there is a carry multiplexer (MUXCY) and a dedicated XOR gate for adding/subtracting the operands with selected carry bits. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade function generators for implementing wide logic functions.