The Configurable Logic Block (CLB) is the main resource for implementing general-purpose combinatorial and sequential circuits. Synthesis tools automatically use the highly efficient logic, arithmetic, and memory features of the UltraScale architecture. These features can also be directly instantiated for greater control over the implementation. The CLB is made up of the logic elements themselves, which are grouped together in a slice, along with the interconnect routing resources to connect the logic elements. Utilization of slices, their placement in the device, and routing between them is best left to the automatic tools, but knowing the UltraScale architecture helps you create more optimal designs.
This user guide provides the necessary CLB details for designers to produce code that uses all of the CLB capabilities. This overview section introduces the most commonly used CLB resources. Later chapters include further detail for optimizing a design to improve density, performance, or power.
The UltraScale architecture CLBs provide advanced, high-performance, low-power programmable logic with:
- Real 6-input look-up table (LUT) capability.
- Dual LUT5 (5-input LUT) option.
- Distributed memory and shift register logic (SRL) ability.
- Dedicated high-speed carry logic for arithmetic functions.
- Wide multiplexers for efficient utilization.
- Dedicated storage elements that can be configured as flip-flops or latches with flexible control signals.
Each UltraScale architecture CLB contains one slice. Each slice provides eight 6-input LUTs and sixteen flip-flops. Slices easily connect to each other to create larger functions. The slices and their CLBs are arranged in columns throughout the device, with the size and number of columns increasing with density.
The UltraScale architecture LUTs can be configured as shown in the following figure.
- A 6-input LUT with one output.
- Two 5-input LUTs with separate outputs but common addresses or logic inputs.
Each LUT output can connect to slice outputs, or optionally be registered in a flip-flop or latch. The storage elements can also be driven by direct inputs to the slice (X and I), or by the results of the internal carry logic or wide multiplexers. See the following figure. The storage elements have a clock enable input, along with an initialization signal that can be programmed as either synchronous or asynchronous, and as set or reset.
Dedicated carry logic improves the performance of arithmetic functions such as adders, counters, and multipliers. Carry logic consists of dedicated carry-lookahead gates, multiplexers, and routing that are independent of the general-purpose logic resources while providing both higher density and increased performance. Carry logic is often inferred for smaller arithmetic functions. Larger, more complex arithmetic functions can use the dedicated DSP block. See the UltraScale Architecture DSP Slice User Guide (UG579).
Each 6-input LUT can implement a 4:1 multiplexer (MUX). Dedicated multiplexers in the slices combine the LUTs together to create even wider functions without having to connect to another slice. All the LUTs in a slice can be combined together as a 32:1 MUX in one level of logic.
Eight 6-input LUTs and their sixteen storage elements, as well as the multiplexers and arithmetic carry logic, form a slice, as shown in the following figure. Each 6-input LUT and set of associated flip-flops and other logic are labeled A to H from bottom to top.
There are two types of slices in the UltraScale architecture, with different ratios of the two types by device. The SLICEL (logic) has all the LUT and storage element resources shown, along with the carry logic and wide multiplexers. A SLICEM (memory) can also use the LUTs as distributed 64-bit RAM, by adding a separate write address (WA), write enable (WE), and clock signal. The LUT can be configured as either a 64 x 1 or 32 x 2 memory. The direct inputs X and I serve as the data inputs. See the following figure.
The distributed RAM can be combined across the eight LUTs in the SLICEM to create memories of up to 512 bits. The SLICEM shares a common write address and write clock across all 8 LUTs. The SLICEM write enable is also shared but can be used in combination with three other slice inputs for more flexibility. Multiple SLICEM can be combined together to create memories larger than 512 bits. Dedicated block RAM is also available for larger memories. See the UltraScale Architecture Memory Resources User Guide (UG573).
Each LUT in a SLICEM can also be used as a 32-bit shift register (SRL32). Combining the LUTs allows up to a 256-bit shift register in one SLICEM, compared to the 16 dedicated flip-flops per slice.
More details on each of these features are provided in CLB Functionality.