The following table describes the UltraRAM attributes.
| Attributes | Values | Default | Type | Description |
|---|---|---|---|---|
| AUTO_SLEEP_LATENCY | 3 to 15 | 8 | DECIMAL | Sets the latency requirement for UltraRAM to sleep mode |
|
AVG_CONS_INACTIVE_CYCLES |
10 to 100000 | 10 | DECIMAL | Sets the average consecutive inactive cycles in sleep mode. When in sleep mode, this is defined as the average number of cycles with no read/write operation on either port. Used by the power reporting tools. Set by the user. |
| BWE_MODE_A | PARITY_INTERLEAVED, PARITY_INDEPENDENT | PARITY_INTERLEAVED | STRING | Port A byte write control for either 1 byte/1 bit 8 bytes/1 byte parity |
| BWE_MODE_B | PARITY_INTERLEAVED, PARITY_INDEPENDENT | PARITY_INTERLEAVED | STRING | Port B byte write control for either 1 byte/1 bit 8 bytes/1 byte parity |
| CASCADE_ORDER_A | NONE, FIRST, MIDDLE, LAST | NONE | STRING | Port A position of UltraRAM block in the cascade chain |
| CASCADE_ORDER_B | NONE, FIRST, MIDDLE, LAST | NONE | STRING | Port B position of UltraRAM block in the cascade chain |
| EN_AUTO_SLEEP_MODE | FALSE, TRUE | FALSE | STRING | Enables UltraRAM to automatically go into power saving mode |
| EN_ECC_RD_A | FALSE, TRUE | FALSE | STRING | Port A ECC decoder used for data read or not |
| EN_ECC_RD_B | FALSE, TRUE | FALSE | STRING | Port B ECC decoder used for data read or not |
| EN_ECC_WR_A | FALSE, TRUE | FALSE | STRING | Port A ECC encoder used for data write or not |
| EN_ECC_WR_B | FALSE, TRUE | FALSE | STRING | Port B ECC encoder used for data write or not |
| IREG_PRE_A | FALSE, TRUE | FALSE | STRING | Inserts port A data, address, and control input pipeline registers |
| IREG_PRE_B | FALSE, TRUE | FALSE | STRING | Inserts port B data, address, and control input pipeline registers |
| IS_CLK_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Optional inverter for CLK |
| IS_EN_A_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port A optional inverter for EN |
| IS_EN_B_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port B optional inverter for EN |
| IS_RDB_WR_A_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port A optional inverter for RDB_WR |
| IS_RDB_WR_B_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port B optional inverter for RDB_WR |
| IS_RST_A_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port A optional inverter for reset input |
| IS_RST_B_INVERTED | 1’b0 to 1’b1 | 1’b0 | BINARY | Port B optional inverter for reset input |
| MATRIX_ID | Custom label | NONE | STRING | Custom label (string) to set a matrix ID name used by the power reporting tools to tag all of the UltraRAM blocks that belong to a cascade chain or matrix. Assign different names to each matrix. Single UltraRAM instances do not require a label. Used by the power reporting tools. Set by the user or synthesis tools. |
| NUM_URAM_IN_MATRIX | 1 to 2048 | 1 | DECIMAL | Defines the cascade/matrix size (the number of UltraRAMs in a matrix). Attach to the instances in a particular matrix. For single instances, set to 1. Used by the power reporting tools. Set by the user or synthesis tools. |
| NUM_UNIQUE_SELF_ADDR_A | 1 to 2048 | 1 | DECIMAL | The number of unique SELF_ADDR_A UltraRAM blocks in a cascade chain or matrix. Typically equal to the number of blocks in a cascade chain or matrix. In the broadcast case, the number could be smaller due to common SELF_ADDR_A settings. Used by the power reporting tools. Set by the user or synthesis tools. |
| NUM_UNIQUE_SELF_ADDR_B | 1 to 2048 | 1 | DECIMAL | The number of unique SELF_ADDR_B UltraRAM blocks in a cascade chain or matrix. Typically equal to the number of blocks in a cascade chain or matrix. In the broadcast case, the number is smaller due to common SELF_ADDR_B settings. Used by the power reporting tools. Set by the user or synthesis tools. |
| OREG_A | FALSE, TRUE | FALSE | STRING | Inserts port A SRAM array output optional pipeline register |
| OREG_B | FALSE, TRUE | FALSE | STRING | Inserts port B SRAM array output optional pipeline register |
| OREG_ECC_A | FALSE, TRUE | FALSE | STRING | Inserts port A ECC decoder output optional pipeline register |
| OREG_ECC_B | FALSE, TRUE | FALSE | STRING | Inserts port B ECC decoder output optional pipeline register |
| REG_CAS_A | FALSE, TRUE | FALSE | STRING | Inserts port A cascade data input and data output pipeline registers |
| REG_CAS_B | FALSE, TRUE | FALSE | STRING | Inserts port B cascade data input and data output pipeline registers |
| RST_MODE_A | SYNC, ASYNC | SYNC | STRING | Port A reset mode |
| RST_MODE_B | SYNC, ASYNC | SYNC | STRING | Port B reset mode |
| SELF_ADDR_A | 11'h000 to 11'h7ff | 11'h000 | HEX | Port A self-address value |
| SELF_ADDR_B | 11'h000 to 11'h7ff | 11'h000 | HEX | Port B self-address value |
| SELF_MASK_A | 11'h000 to 11'h7ff | 11'h7ff | HEX | Port A self-address mask |
| SELF_MASK_B | 11'h000 to 11'h7ff | 11'h7ff | HEX | Port B self-address mask |
| USE_EXT_CE_A | FALSE, TRUE | FALSE | STRING | Port A attribute to allow either internal or external control for the CE pins on all output pipeline registers |
| USE_EXT_CE_B | FALSE, TRUE | FALSE | STRING | Port B attribute to allow either internal or external control for the CE pins on all output pipeline registers |
Note: The URAM288_BASE primitive does not have any of the cascade
attributes.