Revision History - Revision History - UG573

UltraScale Architecture Memory Resources User Guide (UG573)
Document ID
UG573
Release Date
2025-11-18
Revision
1.14 English

The following table shows the revision history for this document.

Section Revision Summary
11/18/2025 Version 1.14
Cascadable Block RAM Updated description of RDCLK and WRCLK inputs for cascaded block RAMs.
INIT_FILE Replaced reference to UG898 with UG1579 and UG1580.
Byte-Wide Write Enable Changed RAMB36E1 and RAMB18E1 to RAMB36E2 and RAMB18E2, respectively.
Reset Added sentence about RST being asserted for longer than one clock cycle.
09/24/2021 Version 1.13
Address Collision Revised WE description.
Block RAM ECC VHDL and Verilog Templates Revised section.
References Added UG901.
03/17/2021 Version 1.12
Address Collision Added additional bullet to list before table.
Table 1 Revised values, default, and type for IS_XX_INVERTED attributes.
08/18/2020 Version 1.11
Block RAM Summary, Common-Clock/Single-Clock FIFO, and Block RAM and UltraRAM Differences Revised important notes.
02/04/2019 Version 1.10
Address Collision Added information on common and independent clocks.
Simple Dual-Port Block RAM Revised port A to write port and port B to read port.
UltraRAM Key Features Removed content clear.
02/09/2018 Version 1.9
Table 1 Revised description for EN_A and EN_B ports.
Figure 1 Revised figure.
11/14/2017 Version 1.8
Common-Clock/Single-Clock FIFO Revised important note.
Set Enable Auto Sleep Mode – EN_AUTO_SLEEP_MODE Added note.
UltraRAM Summary Revised section.
Auto Sleep Waveforms Removed Figure 2-28 and associated verbiage.
08/10/2017 Version 1.7
Common-Clock/Single-Clock FIFO Added important note.
ECC Encode-Only Read Revised section.
05/04/2017 Version 1.6
Table 1 Updated table.
03/15/2017 Version 1.5
Block RAM Summary Revised important note.
Table 1 Added note 2.
Reset – RST_A, RST_B Revised section.
UltraRAM Timing Diagrams Added section.
07/20/2016 Version 1.4
Differences from Previous Generations, Synchronous Dual-Port and Single-Port RAMs, Power Saving – RDADDRCHANGE[A|B], Power Gating Enable Input – SLEEP, Data-Out Buses – DOUT_A, DOUT_B, Read Status Output – RDACCESS_A, RDACCESS_B, Optional Cascade Register Stage – REG_CAS_[A|B], Cascading UltraRAM and Matrix Configurations, and Cascade User Attributes Revised sections.
Table 1 and Table 1 Added note to tables.
Table 1 Updated table.
AVG_CONS_INACTIVE_CYCLES, MATRIX_ID, NUM_URAM_IN_MATRIX, and NUM_UNIQUE_SELF_ADDR_A|B Attributes Added sections.
Figure 1 and Figure 1 Updated figures.
11/24/2015 Version 1.3
General updates
  • Added UltraScale+ device information.
  • Reorganized user guide by incorporating previous Chapter 2 (Built-in FIFO) and Chapter 3 (Built-in Error Correction) into Block RAM Resources, and adding a new UltraRAM Resources.
Introduction to the UltraScale Architecture Updated section to include UltraScale+ information.
Block RAM Summary Updated important note in section.
RAMB18/36 Unused Inputs Added introductory paragraph to section.
02/24/2015 Version 1.2
Block RAM Resources Updated Content Initialization – INIT_xx.
08/14/2014 Version 1.1
General updates Removed PROG_EMPTY_THRESH Range for FIFO18E2/FIFO36E2 and PROG_FULL_THRESH Range for FIFO18E2/FIFO36E2 tables in Chapter 2.
Block RAM Summary Updated bullet 11.
Table 2
  • Changed description of CASDINPA[3:0] and CASDINB[31:0].
  • Updated CASOUTSBITERR, CASINDBITERR, and CASOUTSBITERR.
Table 1 Updated description of DOB_REG.
Figure 1 Updated WDADDREN input.
Table 1 Added table.
Cascadable Block RAM Updated section.
SLEEP and Power Saving – SLEEP_ASYNC Minor changes in sections.
Common-Clock/Single-Clock FIFO Minor changes to descriptions.
Figure 1 and Figure 2 Added SLEEP input.
Table 1 Added SLEEP port and changed descriptions of CASOREGIMUX, CASOREGIMUXEN, CASDOMUX, and CASDOMUXEN.
Table 2 Updated Table 1-26.
Table 1 Added table.
PROG_EMPTY_THRESH, PROG_FULL_THRESH, and REGISTER_MODE Updated sections.
12/10/2013 Version 1.0
Initial release. Initial release.