Important: The reset spec and implementation has been
changed completely compared to 7 series FIFOs. RST is
synchronous to WRCLK. To assert RST, it must be asserted for one setup time prior to the
rising edge of WRCLK. RST has an optional inversion at the input.
If RST is asserted, the WRRSTBUSY output asserts immediately after the rising edge of WRCLK, and remains asserted until the reset operation is complete. Following the assertion of WRRSTBUSY, the internal reset is synchronized to the RDCLK domain. Upon arrival in the RDCLK domain, the RDRSTBUSY is asserted, and is held asserted until the resetting of all RDCLK domain signals is complete, then RDRSTBUSY is deasserted. In common-clock Mode, this logic is simplified because the clock domain crossing is not required.
If RST is asserted for longer than one clock cycle, the WRRSTBUSY and RDRSTBUSY outputs might toggle on and off until RST is deasserted.