Register Enable for OREG_ECC Pipeline Stage – OREG_ECC_CE_A, OREG_ECC_CE_B - Register Enable for OREG_ECC Pipeline Stage – OREG_ECC_CE_A, OREG_ECC_CE_B - UG573

This register enable pin controls the ECC optional output register. When this register is enabled using the OREG_ECC_A/B attribute, and the corresponding CE input is High, the read data is stored in the register at the rising clock edge. The polarity of CE inputs is not configurable (active High).