Unused input pins require a certain, defined constant input value for the block RAM to function properly. If left unconnected (Verilog), the AMD Vivado™ tools automatically tie them to the appropriate constant value. However, if the inputs are connected to a constant in the design (VHDL), then the values listed in the following table are required.
The unused inputs are shown in the following table.
| RAMB18/36 | Constant | Comments |
|---|---|---|
| ADDRENA | 1 | |
| ADDRENB | 1 | |
| CLKARDCLK | 0 | |
| CLKBRDCLK | 0 | |
| CLKAWRCLK | 0 | |
| CLKBWRCLK | 0 | |
| ENARDEN | 0 | |
| ENBWREN | 0 | |
| REGCEAREGCE | 1 | AMD recommends setting to 0 when DOA_REG = 0 for power saving. |
| REGCEB | 1 | AMD recommends setting to 0 when DOB_REG = 0 for power saving. |
| REGCLKARDRCLK | 0 | |
| REGCLKB | 0 | |
| RSTREGARSTREG | 0 | |
| RSTREGB | 0 | |
| RSTRAMARSTRAM | 0 | |
| RSTRAMB | 0 | |
| RSTRAMARSTRAM | 0 | |
| RSTRAMB | 0 | |
| SLEEP | 0 | |
| WEA<3:0> | 1 | TDP: When not using port A for write, (WRITE_WIDTH_A = 0), WEA<0> must be connected to 0. |
| WEBWE<7:0> | 1 | TDP: When not using port B for write (WRITE_WIDTH_B=0), WEB<0> must be connected to 0. |
| CASDOMUXA | 0 | |
| CASDOMUXB | 0 | |
| CASOREGIMUXA | 0 | |
| CASOREGIMUXB | 0 | |
| CASDIMUXA | 0 | |
| CASDIMUXB | 0 | |
| CASDOMUXEN_A | 1 | |
| CASDOMUXEN_B | 1 | |
| CASOREGIMUXEN_A | 1 | |
| CASOREGIMUXEN_B | 1 | |
| INJECTSBITERR | 0 | |
| INJECTDBITERR | 0 |