Many designs use block RAMs to implement FIFOs. Common-clock or independent-clock FIFOs can be easily implemented with the dedicated logic in the block RAM. This eliminates the need for additional CLB logic for counter, comparator, or status flag generation, and uses one block RAM resource per FIFO. Both standard and first-word fall-through (FWFT) modes are supported.
The FIFO can be configured as an 18 Kb or 36 Kb memory. For the 18 Kb mode, the supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36. The supported configurations for the 36 Kb FIFO are 8K x 4, 4K x 9, 2K x 18, 1K x 36, and 512 x 72. The FIFO ports can now be configured in an asymmetrical fashion.
The block RAM can be configured as a first-in/first-out (FIFO) memory with common or independent read and write clocks. Port A of the block RAM is used as a FIFO read port, and Port B is a FIFO write port. Data is read from the FIFO on the rising edge of the read clock and written to the FIFO on the rising edge of the write clock.