Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) - Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B])

Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) - Output Latches/Registers Synchronous Set/Reset (SRVAL_[A|B]) - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

The SRVAL (single-port) or SRVAL_A and SRVAL_B (dual-port) attributes define output latch values when the RSTRAM/RSTREG input is asserted. The width of the SRVAL (SRVAL_A and SRVAL_B) attribute is the port width, as shown in the following table. These attributes are hex-encoded bit vectors and the default value is 0. This attribute sets the value of the output register when the optional output register attribute is set. When the register is not used, the latch gets set to the SRVAL instead. The following tables show how the SRVAL and INIT bit locations map to the DOUT outputs for the block RAM primitives and the SDP macro.

Table 1. RAMB18E2 and RAMB36E2, SRVAL and INIT Mapping for Port A and Port B
Port Width	SRVAL/INIT_(A/B) Full Width	SRVAL/INIT_(A/B) Mapping to DOUT		SRVAL/INIT_(A/B) Mapping to DOUTP
Port Width	SRVAL/INIT_(A/B) Full Width	DOUTADOUT/ DOUTBDOUT	(SRVAL/INIT)_(A/B)	DOUTP(A/B)/DOUTP	SRVAL/INIT_(A/B)
1	[0]	[0]	[0]	N/A	N/A
2	[1:0]	[1:0]	[1:0]	N/A	N/A
4	[3:0]	[3:0]	[3:0]	N/A	N/A
9	[8:0]	[7:0]	[7:0]	[0]	[8]
18	[17:0]	[15:0]	[15:0]	[1:0]	[17:16]
36 (only for RAMB36E2)	[35:0]	[31:0]	[31:0]	[3:0]	[35:32]

Table 2. SDP Mapping for RAMB18E2 and RAMB36E2
Port Width	SRVAL/INIT Full Width	SRVAL/INIT Mapping to DOUT		SRVAL/INIT Mapping to DOUTP
Port Width	SRVAL/INIT Full Width	DOUT	SRVAL/INIT	DOUTP	SRVAL/INIT
36-bit wide RAMB18E2	[35:0]	[31:0]	[33:18]/[15:0]	[3:0]	[35:34]/[17:16]
72-bit wide RAMB36E2	[71:0]	[63:0]	[67:36]/[31:0]	[7:0]	[71:68]/[35:32]