Optional Output Register Stage – OREG_[A|B] - Optional Output Register Stage

Optional Output Register Stage – OREG_[A|B] - Optional Output Register Stage – OREG_[A|B] - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

This attribute determines if the SRAM array output has a pipeline stage enabled or not.