Optional Input Register Stage – IREG_PRE_[A|B] - Optional Input Register Stage – IREG_PRE_[A|B] - UG573

This attribute determines if EN/RDB_WR/BWE/ADDR/DIN/INJECT_SBITERR/INJECT_DBITERR UltraRAM inputs have their respective input pipeline registers enabled or not. IREG_PRE and REG_CAS are mutually exclusive except as noted under Optional Cascade Register Stage – REG_CAS_[A|B]. See Figure 1.