Optional ECC Output Register Stage – OREG_ECC_[A|B] - Optional ECC Output Register Stage – OREG_ECC_[A|B] - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID
UG573
Release Date
2025-11-18
Revision
1.14 English

This attribute determines if the ECC error and data outputs of the ECC decode logic have the pipeline registers enabled or not.