The independent-clock FIFO (also referred to as a dual-clock or sometimes asynchronous FIFO) is a first-in/first-out queue where the write interface and the read interface exist in different clock domains. To configure the FIFO as an independent-clock FIFO, the attribute CLOCK_DOMAINS should be set to INDEPENDENT.
The independent-clock FIFO offers a simple write interface and a simple read interface, both of which could be free-running clocks with no frequency or phase relationship between the clocks. As such, it is ideal for situations where:
- WRCLK and RDCLK have different but related frequencies
- WRCLK and RDCLK are out-of-phase with each other
- WRCLK and RDCLK are completely asynchronous (have no relationship)
The independent-clock FIFO can support clock frequencies up to the specified maximum limit. The dual-clock FIFO design avoids ambiguity, glitches, or metastability problems, and provides a convenient way to pass data between differing clock domains.
The write interface is synchronous to the WRCLK domain, writing the data word available on DIN into the FIFO whenever WREN is active one setup time prior to the rising edge of WRCLK.
The read interface is synchronous to the RDCLK domain, triggering a read operation in the FIFO whenever RDEN is active prior to the rising edge of RDCLK, and presenting the next word of data on DOUT following the rising edge of RDCLK in standard mode.
Due to the internal synchronization between the WRCLK domain and the RDCLK domain, certain transitions take an extended number of clock cycles. For example, it takes several clock cycles (both WRCLK and RDCLK clock cycles) for the write operation to synchronize to the RDCLK domain. Only after the write operation has synchronized to the RDCLK domain is that write operation reflected in the status of the RDCLK outputs EMPTY and PROGEMPTY, possibly causing those flags to deassert.
Similarly, the internal synchronization between the RDCLK domain and the WRCLK domain also takes an extended number of clock cycles. For example, it takes several clock cycles (both RDCLK and WRCLK clock cycles) for the read operation to synchronize to the WRCLK domain. Only after the read operation has synchronized to the WRCLK domain is that read operation reflected in the status of the WRCLK outputs FULL and PROGFULL, possibly causing those flags to deassert.
All of the FIFO’s inputs and outputs are synchronous to either the WRCLK or RDCLK domain. Due to the uncertainty of two unrelated clock domains, one memory location is reserved in the implementation to prevent errors.