INIT and SRVAL - INIT and SRVAL - UG573

UltraScale Architecture Memory Resources User Guide (UG573)
Document ID
UG573
Release Date
2025-11-18
Revision
1.14 English

INIT defines the values of the output latches (DOUT and DOUTP) or output register values after configuration. SRVAL defines values of the output latches or output register when the RST/RSTREG input is asserted. See the following table.

Table 1. FIFO18E2 and FIFO36E2, SRVAL and INIT Mapping
Port Width SRVAL/INIT Full Width SRVAL/INIT Mapping to DOUT SRVAL/INIT Mapping to DOUTP
DOUT SRVAL/INIT DOUTP SRVAL/INIT
1 [0] [0] [0] N/A N/A
2 [1:0] [1:0] [1:0] N/A N/A
4 [3:0] [3:0] [3:0] N/A N/A
9 [8:0] [7:0] [7:0] [0] [8]
18 [17:0] [15:0] [15:0] [1:0] [17:16]
36 [35:0] [31:0] [31:0] [3:0] [35:32]
72 (only for FIFO36E2) [71:0] [63:0] [63:0] [7:0] [71:64]