If FULL is asserted, the FIFO has no room for any additional words to be written to the FIFO, and any additional write operations cause a write error (WRERR=1). When reading from a full FIFO, the number of clock cycles required for the FULL output to deassert depend on the FIFO configuration. For an independent-clocks FIFO, a read operation must be synchronized internally to the WRCLK domain before it can influence the status of the FULL flag, resulting in a latency from the read operation to the deassertion of FULL that is a combination of a few read clocks followed by a few write clocks.
The FULL flag is synchronous to the WRCLK domain and is intended as a handshaking signal for logic writing to the FIFO.