Flag Assertion/Deassertion and Flag Latencies - Flag Assertion/Deassertion and Flag Latencies

Flag Assertion/Deassertion and Flag Latencies - Flag Assertion/Deassertion and Flag Latencies - UG573

UltraScale Architecture Memory Resources User Guide (UG573)

Document ID

UG573

Release Date

2025-11-18

Revision

1.14 English

Flag assertion and deassertion timing depends on the configuration of the FIFO. The common-clock FIFO configuration is not affected by the uncertainty of two unrelated clock domains, and requires no synchronization between clock domains. Therefore, the internal latencies from a write operation to the deassertion of EMPTY or PROGEMPTY, or from a read operation to the deassertion of FULL or PROGFULL, are much faster than in an equivalent independent-clock FIFO. Similarly, a FIFO configured with asymmetric ports has additional latencies depending on the port width ratios of the read and write port. The configuration of the REGISTER_MODE, FIRST_WORD_FALL_THROUGH, and EN_ECC_PIPE attributes can increase the latency from a write operation to the deassertion of EMPTY up to three additional RDCLK cycles.

Independent-clock FIFOs are synchronized between clock domains. Due to this internal synchronization between the WRCLK domain and the RDCLK domain, certain transitions take several clock cycles. For example, it takes several clock cycles (both WRCLK and RDCLK clock cycles) for the write operation to synchronize to the RDCLK domain. Only after the write operation is synchronized to the RDCLK domain is that write operation reflected in the status of the RDCLK outputs EMPTY and PROGEMPTY, and possibly cause these flags to deassert.

Similarly, the internal synchronization between the RDCLK domain and the WRCLK domain also takes several clock cycles. For example, it takes several clock cycles (both RDCLK and WRCLK clock cycles) for the read operation to synchronize to the WRCLK domain. Only after the read operation is synchronized to the WRCLK domain is that read operation reflected in the status of the WRCLK outputs FULL and PROGFULL, and possibly cause these flags to deassert. Due to the clock phase relationship uncertainty in the independent clock FIFO, the deassertion of the flags can vary by one clock cycle.

Table 1. Independent-clock FIFO
	Assertion¹	Deassertion Standard FIFO²	Deassertion FWFT FIFO²
EMPTY	0 RDCLK	1 WRCLK and 4 or 5 RDCLK³	1 WRCLK and 5 or 6 RDCLK³
PROGEMPTY	1 RDCLK	1 WRCLK and 5 or 6 RDCLK	1 WRCLK and 5 or 6 RDCLK
FULL	0 WRCLK	1 RDCLK and 4 or 5 WRCLK	1 RDCLK and 4 or 5 WRCLK
PROGFULL	1 WRCLK	1 RDCLK and 5 or 6 WRCLK	1 RDCLK and 5 or 6 WRCLK
Assertion latency is from the rising edge of the RDCLK/WRCLK with the RD/WR operation enabled if the operation caused the FIFO to go EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag asserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge is required. Deassertion latency starts from the rising edge of the RDCLK/WRCLK to the deassertion of the flag when the FIFO is no longer EMPTY (PROGEMPTY) or FULL (PROGFULL) (after the first read or write) and the read/write operation is enabled. Deassertion occurs after the first rising edge of the clock plus N cycles. N can vary due to the asynchronous nature of the clocks. Registered mode adds one RDCLK clock cycle.

Figure 1. Deassertion and Assertion Latencies of EMPTY and PROGEMPTY for Independent-Clock FIFO

Figure 2. Deassertion and Assertion Latencies of FULL and PROGFULL for Independent-Clock FIFO

The programmable flags in the preceding figures are asserted and deasserted based on their threshold settings and there is no dependency or relationship to the EMPTY/FULL flags.

Table 2. Common-clock FIFO
	Assertion¹	Deassertion Standard FIFO²	Deassertion FWFT FIFO²
EMPTY	0 RDCLK	0 WRCLK ³	1 WRCLK ³
PROGEMPTY	1 RDCLK	1 WRCLK	1 WRCLK
FULL	0 WRCLK	0 RDCLK	0 RDCLK
PROGFULL	1 WRCLK	1 RDCLK	1 RDCLK
Assertion latency is from the rising edge of the RD/WR with the RD/WR operation enabled if the operation caused the FIFO to go EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag asserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge is required. Deassertion latency is from the rising edge of the clock when the operation is enabled to the deassertion of the flag when the FIFO is no longer EMPTY (PROGEMPTY) or FULL (PROGFULL). A latency of zero indicates that the flag deasserts immediately following the rising edge of the clock, and a latency of one indicates that one extra rising clock edge is required. Registered mode adds one RDCLK clock cycle.

Figure 3. Deassertion and Assertion Latencies of EMPTY and PROGEMPTY for Common-Clock FIFO

Figure 4. Deassertion and Assertion Latencies of FULL and PROGFULL for Common-Clock FIFO

The programmable flags in the preceding figures are asserted and deasserted based on their threshold settings and there is no dependency or relationship to the EMPTY/FULL flags.