FIFO Port Width and Depth - FIFO Port Width and Depth - UG573

UltraScale Architecture Memory Resources User Guide (UG573)
Document ID
UG573
Release Date
2025-11-18
Revision
1.14 English

The FIFOs support asymmetric read and write ports based on the block RAM’s asymmetric port capability to support different port widths for each port. The FIFO18E2 supports independent read/write port width combinations of 4, 8, 16, and 32, which can be expanded to 9, 18, and 36 when utilizing the DINP bits. The FIFO36E2 supports independent read/write port width combinations of 4, 8, 16, 32, and 64, which can be expanded to 9, 18, 36, and 72 when utilizing the DINP bits.

When considering features such as output register stages, FWFT mode, or asymmetric ports, FIFO depth varies. When using asymmetric port widths, the FIFO depth differs depending on the number of write words in the WRCLK domain and the number of read words in the RDCLK domain.

FIFO depth in the WRCLK domain is the number of write words that, when written to a FIFO, causes it to go FULL. In a special case, if the read port is narrower than the write port, it is possible that a partial word exists in the FIFO, causing FULL to assert one clock earlier than expected.

FIFO depth in the RDCLK domain is the number of read words that would be in the FIFO if the FIFO were FULL. Because the read port width might not be the same as the write port width, the depth differs when expressed in the RDCLK domain. Also, in a special case where the write port is narrower than the read port, it is possible that a partial word exists in the FIFO that is not available to be read and therefore does not count toward the FIFO depth in the RDCLK domain.

The FIFO depth can be used to understand and calculate:

  • When using WRCOUNT, the depth determines how many more writes can be performed before the FIFO goes FULL (in the WRCLK domain). This calculation is:
    • “FIFO Depth” minus “Number of Words in FIFO” where the number of words available in the FIFO is given by the WRCOUNT (for WRCOUNT_TYPE SIMPLE_DATACOUNT mode for standard FIFOs with no output stages, or EXTENDED_DATACOUNT count mode when using output stages or FWFT).
  • “FIFO Depth” minus “Number of Words in FIFO” where the number of words available in the FIFO is given by the WRCOUNT (for WRCOUNT_TYPE SIMPLE_DATACOUNT mode for standard FIFOs with no output stages, or EXTENDED_DATACOUNT count mode when using output stages or FWFT).
  • How to calculate the PROG_FULL_THRESH to set the threshold at a specific distance from FULL.
  • Determine the range of PROG_FULL_THRESH.
  • Determine the range of PROG_EMPTY_THRESH.
  • Determine all cases of FULL.

The following tables list the FIFO depths in both the WRCLK and RDCLK domains for all possible FIFO configurations and widths.

Note: The tables do not cover the EN_ECC_PIPE = TRUE configurations, which increase read port depth by 1.
Table 1. Independent Clocks FIFO Port Width and Depths – FIFO36E2
 

Latch Mode

(REGISTER_MODE = "UNREGISTERED")

Register Mode

(REGISTER_MODE = "REGISTERED")
Standard FWFT Standard FWFT
Write Port Width

Read Port Width

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth
4 4 8191 8191 8192 8192 8192 8192 8193 8193
4 8 8191 4095 1 8193 4096 1 8193 4096 1 8195 4097 1
4 16 8191 2047 1 8195 2048 1 8195 2048 1 8199 2049 1
4 32 8191 1023 1 8199 1024 1 8199 1024 1 8207 1025 1
4 64 8191 511 1 8207 512 1 8207 512 1 8223 513 1
8 4 4095 8190 4095 2 8191 4095 2 8191 4096 8192
9 9 4095 4095 4096 4096 4096 4096 4097 4097
9 18 4095 2047 1 4097 2048 1 4097 2048 1 4099 2049 1
9 36 4095 1023 1 4099 1024 1 4099 1024 1 4103 1025 1
9 72 4095 511 1 4103 512 1 4103 512 1 4111 513 1
16 4 2047 8188 2047 2 8189 2047 2 8189 2047 2 8190
18 9 2047 4094 2047 2 4095 2047 2 4095 2048 4096
18 18 2047 2047 2048 2048 2048 2048 2049 2049
18 36 2047 1023 1 2049 1024 1 2049 1024 1 2051 1025 1
18 72 2047 511 1 2051 512 1 2051 512 1 2055 513 1
32 4 1023 8184 1023 2 8185 1023 2 8185 1023 2 8186
36 9 1023 4092 1023 2 4093 1023 2 4093 1023 2 4094
36 18 1023 2046 1023 2 2047 1023 2 2047 1024 2048
36 36 1023 1023 1024 1024 1024 1024 1025 1025
36 72 1023 511 1 1025 512 1 1025 512 1 1027 513 1
64 4 511 8176 511 2 8177 511 2 8177 511 2 8178
72 9 511 4088 511 2 4089 511 2 4089 511 2 4090
72 18 511 2044 511 2 2045 511 2 2045 511 2 2046
72 36 511 1022 511 2 1023 511 2 1023 512 1024
72 72 511 511 512 512 512 512 513 513
  1. When the read port depth has a fractional part, the read depth value is rounded down. The FIFO does not allow partial words to be read from the FIFO, so a partial word can exist in the FIFO even when the FIFO is EMPTY. Therefore, one or more writes might be needed before the final data in the FIFO can be read. When the FIFO is FULL, a single read deasserts FULL, after which two or more write operations are required to get it back to FULL again.
  2. When the write port depth has a fractional part, the write depth value is rounded down. Because it takes multiple reads to read a complete write word, there might be partial write words in the FIFO at some points in time. If FULL, one or more additional read operations might free up enough space to make room for an additional write operation.
Table 2. Common-Clock FIFO Port Width and Depths – FIFO36E2
 

Latch Mode

(REGISTER_MODE = "UNREGISTERED")

Register Mode

(REGISTER_MODE = "REGISTERED")
Standard FWFT Standard FWFT
Write Port Width

Read Port Width

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth
4 4 8192 8192 8193 8193 8193 8193 8194 8194
4 8 8192 4096 8194 4097 8194 4097 8196 4098
4 16 8192 2048 8196 2049 8196 2049 8200 2050
4 32 8192 1024 8200 1025 8200 1025 8208 1026
4 64 8192 512 8208 513 8208 513 8224 514
8 4 4096 8192 4096 1 8193 4096 1 8193 4097 8194
9 9 4096 4096 4097 4097 4097 4097 4098 4098
9 18 4096 2048 4098 2049 4098 2049 4100 2050
9 36 4096 1024 4100 1025 4100 1025 4104 1026
9 72 4096 512 4104 513 4104 513 4112 514
16 4 2048 8192 2048 1 8193 2048 1 8193 2048 1 8194
18 9 2048 4096 2048 1 4097 2048 1 4097 2049 4098
18 18 2048 2048 2049 2049 2049 2049 2050 2050
18 36 2048 1024 2050 1025 2050 1025 2052 1026
18 72 2048 512 2052 513 2052 513 2056 514
32 4 1024 8192 1024 1 8193 1024 1 8193 1024 1 8194
36 9 1024 4096 1024 1 4097 1024 1 4097 1024 1 4098
36 18 1024 2048 1024 1 2049 1024 1 2049 1025 2050
36 36 1024 1024 1025 1025 1025 1025 1026 1026
36 72 1024 512 1026 513 1026 513 1028 514
64 4 512 8192 512 1 8193 512 1 8193 512 1 8194
72 9 512 4096 512 1 4097 512 1 4097 512 1 4098
72 18 512 2048 512 1 2049 512 1 2049 512 1 2050
72 36 512 1024 512 1 1025 512 1 1025 513 1026
72 72 512 512 513 513 513 513 514 514
  1. When the write port depth has a fractional part, the write depth value is rounded down. Because it takes multiple reads to read a complete write word, there might be partial write words in the FIFO at some points in time. If FULL, one or more additional read operations might free up enough space to make room for an additional write operation.
Table 3. Independent-Clock FIFO Port Width and Depths – FIFO18E2
 

Latch Mode

(REGISTER_MODE = "UNREGISTERED")

Register Mode

(REGISTER_MODE = "REGISTERED")
Standard FWFT Standard FWFT
Write Port Width

Read Port Width

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth
4 4 4095 4095 4096 4096 4096 4096 4097 4097
4 8 4095 2047 1 4097 2048 1 4097 2048 1 4099 2049 1
4 16 4095 1023 1 4099 1024 1 4099 1024 1 4103 1025 1
4 32 4095 511 1 4103 512 1 4103 512 1 4111 513 1
8 4 2047 4094 2047 2 4095 2047 2 4095 2048 4096
9 9 2047 2047 2048 2048 2048 2048 2049 2049
9 18 2047 1023 1 2049 1024 1 2049 1024 1 2051 1025 1
9 36 2047 511 1 2051 512 1 2051 512 1 2055 513 1
16 4 1023 4092 1023 2 4093 1023 2 4093 1023 2 4094
18 9 1023 2046 1023 2 2047 1023 2 2047 1024 2048
18 18 1023 1023 1024 1024 1024 1024 1025 1025
18 36 1023 511 1 1025 512 1 1025 512 1 1027 513 1
32 4 511 4088 511 2 4089 511 4089 511 2 4090
36 9 511 2044 511 2 2045 511 2 2045 511 2 2046
36 18 511 1022 511 2 1023 511 2 1023 512 1024
36 36 511 511 512 512 512 2 512 513 513
  1. When the read port depth has a fractional part, the read depth value is rounded down. The FIFO does not allow partial words to be read from the FIFO, so a partial word can exist in the FIFO even when the FIFO is EMPTY. Therefore, one or more writes might be needed before the final data in the FIFO can be read. When the FIFO is FULL, a single read deasserts FULL, after which two or more write operations are required to get it back to FULL again.
  2. When the write port depth has a fractional part, the write depth value is rounded down. Because it takes multiple reads to read a complete write word, there might be partial write words in the FIFO at some points in time. If FULL, one or more additional read operations might free up enough space to make room for an additional write operation.
Table 4. Common-Clock FIFO Port Width and Depths – FIFO18E2
 

Latch Mode

(REGISTER_MODE = "UNREGISTERED")

Register Mode

(REGISTER_MODE = "REGISTERED")
Standard FWFT Standard FWFT
Write Port Width

Read Port Width

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth

 Write Port Depth

Read Port Depth
4 4 4096 4096 4097 4097 4097 4097 4098 4098
4 8 4096 2048 4098 2049 4098 2049 4100 2050
4 16 4096 1024 4100 1025 4100 1025 4104 1026
4 32 4096 512 4104 513 4104 513 4112 514
8 4 2048 4096 2048 1 4097 2048 1 4097 2049 4098
9 9 2048 2048 2049 2049 2049 2049 2050 2050
9 18 2048 1024 2050 1025 2050 1025 2052 1026
9 36 2048 512 2052 513 2052 513 2056 514
16 4 1024 4096 1024 1 4097 1024 1 4097 1024 1 4098
18 9 1024 2048 1024 1 2049 1024 1 2049 1025 2050
18 18 1024 1024 1025 1025 1025 1025 1026 1026
18 36 1024 512 1026 513 1026 513 1028 514
32 4 512 4096 512 1 4097 512 1 4097 512 1 4098
36 9 512 2048 512 1 2049 512 1 2049 512 1 2050
36 18 512 1024 512 1 1025 512 1 1025 513 1026
36 36 512 512 513 513 513 513 514 514
  1. When the write port depth has a fractional part, the write depth value is rounded down. Because it takes multiple reads to read a complete write word, there might be partial write words in the FIFO at some points in time. If FULL, one or more additional read operations might free up enough space to make room for an additional write operation.