FIFO Port Descriptions and Attributes - FIFO Port Descriptions and Attributes

The following table lists the FIFO I/O port names and descriptions.

Table 1. FIFO18E2 and FIFO36E2 Port Names and Descriptions
Port	Direction	Description	Configurations
PROGEMPTY	Output	Programmable flag to indicate the FIFO is almost empty (contains less than or equal to the number of words specified by PROG_EMPTY_THRESH). Synchronous to RDCLK.	All configurations. Controlled by PROG_EMPTY_THRESH.
PROGFULL	Output	Programmable flag to indicate the FIFO is almost full (contains greater than or equal to the number of words specified by PROG_FULL_THRESH). Synchronous to WRCLK.	All configurations. Controlled by PROG_FULL_THRESH.
FIFO18: DIN<31:0> FIFO36: DIN<63:0>	Input	FIFO data input bus. Synchronous to WRCLK.	All configurations, width controlled by WRITE_WIDTH.
FIFO18: DINP<3:0> FIFO36: DINP<7:0>	Input	FIFO parity input bus. Synchronous to WRCLK.	All configurations, width controlled by WRITE_WIDTH.
FIFO18: DOUT<31:0> FIFO36: DOUT<63:0>	Output	FIFO data output bus. Synchronous to RDCLK.	All configurations, width controlled by READ_WIDTH.
FIFO18: DOUTP<3:0> FIFO36: DOUTP<7:0>	Output	FIFO parity output bus. Synchronous to RDCLK.	All configurations, width controlled by READ_WIDTH.
EMPTY	Output	Active-High flag to indicate when the FIFO is empty. Synchronous to RDCLK.	All configurations.
FULL	Output	Active-High flag to indicate when the FIFO is full. Synchronous to WRCLK.	All configurations.
RDCLK	Input	Read clock.	All configurations.
FIFO18: RDCOUNT<12:0> FIFO36: RDCOUNT<13:0>	Output	Output of either the internal FIFO read pointer, or a count of the number of words in the FIFO. Synchronous to RDCLK.	All configurations, output value controlled by RDCOUNT_TYPE.
RDEN	Input	Active-High read enable relative to RDCLK.	All configurations.
RDERR	Output	Indicates that a read operation failed due to the FIFO being EMPTY, or FIFO in a reset condition. Synchronous to RDCLK.	All configurations.
RDRSTBUSY	Output	Active-High indicator that the FIFO is currently in a reset state. Synchronous to RDCLK.	Indicates that the RDCLK domain FIFO logic is currently in a reset state. Any attempt to perform a read operation while RDRSTBUSY = 1 causes a RDERR.
REGCE	Input	Active-High enable for output register stage relative to RDCLK.	Only when REGISTER_MODE = DO_PIPELINED.
RST	Input	Active-High synchronous reset. Synchronous to WRCLK.	RST input. Must be synchronous to the WRCLK domain. RST can be set to 0 when not used.
RSTREG	Input	Active-High enable for output register reset relative to RDCLK.	Only when REGISTER_MODE = DO_PIPELINED.
SLEEP²	Input	Dynamic shutdown power saving. If SLEEP is High, the block RAM memory array is in power-saving mode.	All configurations.
WRCLK	Input	Write clock.	All configurations.
FIFO18: WRCOUNT<12:0> FIFO36: WRCOUNT<13:0>	Output	Output of either the internal FIFO write pointer, or a count of the number of words in the FIFO. Synchronous to WRCLK.	All configurations, output value controlled by WRCOUNT_TYPE.
WREN	Input	Active-High write enable relative to WRCLK.	All configurations.
WRERR	Output	Indicates that a write operation failed due to the FIFO being FULL, or FIFO in a reset condition. Synchronous to WRCLK.	All configurations.
WRRSTBUSY	Output	Active-High indicator that the FIFO is currently in a reset state. Synchronous to WRCLK.	Indicates that the WRCLK domain FIFO logic is currently in a reset state. Any attempt to perform a write operation while WRRSTBUSY = 1 causes a WRERR.
FIFO18: CASDIN<31:0> FIFO36: CASDIN<63:0>	Input	FIFO data input bus from previous FIFO when cascading FIFOs serially or in parallel to extend depth.	Only used when CASCADE_ORDER = MIDDLE, LAST, or PARALLEL.
FIFO18: CASDINP<3:0> FIFO36: CASDINP<7:0>	Input	FIFO parity data input bus from previous FIFO when cascading FIFOs serially or in parallel to extend depth.	Only used when CASCADE_ORDER = MIDDLE, LAST, or PARALLEL.
FIFO18: CASDOUT<31:0> FIFO36: CASDOUT<63:0>	Output	FIFO data output bus to next FIFO when cascading FIFOs serially or in parallel to extend depth.	Only used when CASCADE_ORDER = FIRST, MIDDLE, or PARALLEL.
FIFO18: CASDOUTP<3:0> FIFO36: CASDOUTP<7:0>	Output	FIFO parity data output bus to next FIFO when cascading FIFOs serially or in parallel to extend depth.	Only used when CASCADE_ORDER = FIRST, MIDDLE, or PARALLEL.
CASPRVEMPTY	Input	Cascaded EMPTY input from previous FIFO, used for cascading FIFOs serially to extend depth. Connects to the CASNXTEMPTY of the previous FIFO.	Only used when CASCADE_ORDER = MIDDLE or LAST and cascading FIFOs serially.
CASPRVRDEN	Output	Control output driving the cascaded RDEN input of the previous FIFO, used for cascading FIFOs serially to extend depth. Connects to CASNXTRDEN of the previous FIFO.	Only used when CASCADE_ORDER = MIDDLE or LAST and cascading FIFOs serially.
CASNXTRDEN	Input	Cascaded RDEN input from next FIFO, used for cascading FIFOs serially to extend depth. Connects to CASPRVRDEN of the next FIFO.	Only used when CASCADE_ORDER = FIRST or MIDDLE and cascading FIFOs serially.
CASNXTEMPTY	Output	Cascaded EMPTY output to next FIFO, used for cascading FIFOs serially to extend depth. Connects to CASPRVEMPTY of the next FIFO.	Only used when CASCADE_ORDER = FIRST or MIDDLE and cascading FIFOs serially.
CASOREGIMUX	Input	D input to flip-flop that drives the select line to the cascade multiplexer before the output registers.	Only used when REGISTER_MODE = DO_PIPELINED and CASCADE_ORDER = PARALLEL.
CASOREGIMUXEN	Input	EN input to flip-flop that drives the select line to the cascade multiplexer before the output registers.	Only used when REGISTER_MODE = DO_PIPELINED and CASCADE_ORDER = PARALLEL.
CASDOMUX	Input	D input to flip-flop that drives the select line to the cascade multiplexer on the block RAM outputs.	Only used when CASCADE_ORDER = PARALLEL.
CASDOMUXEN	Input	EN input to the flip-flop that drives the select line to the cascade multiplexer on the block RAM outputs.	Only used when CASCADE_ORDER = PARALLEL.
The ports for using the FIFO36E2 in ECC mode are described in Built-in Error Correction. See block RAM SLEEP pin and attribute descriptions for more information. For the FIFO sleep mode, the assertion and deassertion of RDEN/WREN requirements deviate from the block RAM rules depending on the clock mode (independent/common), read/write clock frequency ratios, and other FIFO configurations, such as FWFT and output/pipeline registers. It is recommended to simulate the design to determine the exact behavior for specific configurations.

The following table lists the FIFO I/O attribute names and descriptions.

Table 2. FIFO18E2 and FIFO36E2 Attributes and Descriptions
Attribute	Values	Default	Description
FIFO18: PROG_EMPTY_THRESH<11:0> FIFO36: PROG_EMPTY_THRESH<12:0>	Decimal User Selectable		Specifies the minimum number of read words in the FIFO at or below which PROGEMPTY is asserted.
FIFO18: PROG_FULL_THRESH<11:0> FIFO36: PROG_FULL_THRESH<12:0>	Decimal User Selectable		Specifies the maximum number of write words in the FIFO at or above which PROGFULL is asserted.
WRITE_WIDTH	Integer 4, 9, 18, 36, 72 (FIFO36)		Indicates the total port width of the DIN and DINP ports.
READ_WIDTH	Integer 4, 9, 18, 36, 72 (FIFO36)		Indicates the total port width of the DOUT and DOUTP ports.
REGISTER_MODE	UNREGISTERED, REGISTERED, DO_PIPELINED	UNREGISTERED	UNREGISTERED: No output register stage. REGISTERED: Output register is controlled automatically by the FIFO controller to behave like an additional FIFO word. DO_PIPELINED: Output register is controlled by external REGCE and RSTREG inputs.
CLOCK_DOMAINS	COMMON, INDEPENDENT	INDEPENDENT	COMMON: Common clock/single clock/synchronous FIFO. INDEPENDENT: Independent clock/dual clock/asynchronous FIFO.
FIRST_WORD_FALL_THROUGH	String: TRUE/FALSE	FALSE	TRUE: Use FWFT FIFO output behavior. FALSE: Use standard FIFO output behavior.
INIT¹	FIFO18: 36-bit hex FIFO36: 72 bit hex	`36'h0000000000` `72'h00000000000000000000`	Specifies the initial value on DOUT after configuration. This initial value always applies to the block RAM/FIFO’s output latches, and also specifies the initial value of the output registers.
SRVAL¹	FIFO18: 36 bit hex FIFO36: 72 bit hex	`36'h0000000000` `72'h00000000000000000000`	Specifies the reset value of the FIFO output bus. This is the reset value of both the RAM output latches and the output registers, regardless of the state of REGISTER_MODE. When REGISTER_MODE = DO_PIPELINED, the RSTREG input resets the DOUT output of the FIFO’s output register stage to this value. Otherwise, DOUT is reset by the FIFO’s RST input.
WRCOUNT_TYPE	RAW_PNTR, SYNC_PNTR, SIMPLE_DATACOUNT, EXTENDED_DATACOUNT	RAW_PNTR	Defines the behavior of the WRCOUNT output. WRCOUNT_TYPE can be configured to provide internal FIFO counter information or a count of the FIFO contents.
RDCOUNT_TYPE	RAW_PNTR, SYNC_PNTR, SIMPLE_DATACOUNT, EXTENDED_DATACOUNT	RAW_PNTR	Defines the behavior of the RDCOUNT output. RDCOUNT_TYPE can be configured to provide internal FIFO counter information or a count of the FIFO contents.
RSTREG_PRIORITY	RSTREG, REGCE	RSTREG	Only used when REGISTER_MODE = DO_PIPELINED. If set to RSTREG, the RSTREG input resets the output register to SRVAL regardless of the state of the REGCE input. If set to REGCE, the RSTREG input resets the output register to SRVAL only if the REGCE input is 1.
CASCADE_ORDER	NONE, FIRST, MIDDLE, LAST, PARALLEL	NONE	Defines the FIFO cascade mode (serial or parallel) and cascade order when cascading FIFOs in series.
The attributes for using the FIFO36E2 in ECC mode are described in Built-in Error Correction.

FIFO Port Descriptions and Attributes - FIFO Port Descriptions and Attributes - UG573

UltraScale Architecture Memory Resources User Guide (UG573)