If EMPTY is asserted, no data is available to be read from the FIFO, and any additional read operations cause a read error (RDERR=1). The relationship of EMPTY to the output data on the DOUT output port depends on whether the FIFO is configured as a standard FIFO or FWFT FIFO.
When writing to an empty FIFO, the number of clock cycles required for the EMPTY output to deassert depends on the FIFO configuration. For an independent-clocks FIFO, a write operation is synchronized internally to the RDCLK domain before it can influence the status of the Empty flag, resulting in a latency from the write operation to the deassertion of EMPTY that is a combination of a few write clocks followed by a few read clocks.
The Empty flag is synchronous to the RDCLK domain and is intended as a handshaking signal for logic reading from the FIFO.