Data-out buses reflect the contents of memory cells referenced by the address bus at the last active clock edge during a read operation. During a write operation or no operation, data-out buses are not changed and the data is preserved from the previous cycle. This applies to both single UltraRAM and cascade/matrix configurations. Similarly for a cascaded UltraRAM, the read output at the end of the cascade chain (at exit point) also holds the previous data. The data bus is 72-bits wide with the lower 64 bits used for data and the upper 8 bits used for parity or as regular data outputs.